ADC accuracy

ENOB & noise — the ideal SNR of an N-bit converter is 6.02·N + 1.76 dB, and the effective number of bits is ENOB = (SINAD − 1.76)/6.02 (Analog Devices MT-003). From measured noise: hold the input steady and take the standard deviation σ of many readings in counts; the effective resolution is N − log₂σ and the noise-free resolution (the bits that never flicker) N − log₂(6.6σ).

Error budget — every error as a fraction of full scale: the reference’s initial tolerance and its drift (tempco × temperature span), the ADC’s gain, offset, and INL, the divider’s ratio error from its resistor tolerances (computed exactly; about 2·tol·(1 − ratio)), and ±½ LSB of quantization. Worst case adds them; RSS (root-sum-square) is the realistic figure for one board. Gain and offset can be calibrated out; INL, drift, and noise cannot.

Loading & settling — an ADC samples by charging a small capacitor C_s through a switch. To settle within ½ LSB the source must charge it in t = (R_source + R_switch)·C_s·ln(2^N+1) during the acquisition time. The tool shows the source resistance a divider presents (and the ratio error from an ADC input resistance), whether it settles, the largest source resistance that would, and the alternative: a capacitor at the pin of at least C_s·2^N+1, which supplies the charge but slows the input to τ = R_source·C. Presets use STM32F1 and ATmega328P datasheet figures.

Oversampling — each extra bit needs four times the samples (Atmel AVR121, Silicon Labs AN118), and averaging n samples gains 10·log₁₀(n) dB — but only with at least about 1 LSB of random noise to dither the input, and it does not remove INL or reference errors.