RISC-V assembly playground

An assembler and a simulator for 32-bit RISC-V (the RV32I base and the M extension for multiply and divide), written for this page and running entirely in it. It aims to make the instruction set visible: what each line turns into, how the bits of an instruction are laid out, what a call does to the stack, and how a simple pipeline would execute the program.

How to use it

Pick an example or type in the Source pane; it assembles as you type and errors appear under the source (click one to jump to the line). The Machine code pane lists every instruction word with its address — pseudo-instructions show what they expand to, so li a0, 0x12345678 becomes a lui and an addi, and call an auipc and a jalr.

Step (F10) runs one instruction, Back undoes it, Run (F5) runs until the program exits, hits a breakpoint or has run five million instructions (an endless loop, probably — Run again to continue). Click the gutter to the left of an address to set a breakpoint. Reset starts over.
Registers shows all 32 with their ABI names (zero, ra, sp, a0…); the ones the last step or run changed are highlighted. Switch between hex, signed and unsigned.
Console shows what the program printed. The ecalls follow RARS’s numbering: put the service in a7 — 1 print integer, 4 print string, 11 print character, 34 hex, 36 unsigned, 5 / 8 / 12 read an integer, line or character (from the input box), 10 exit, 93 exit with a code.
Devices is a memory-mapped peripheral at 0xffff0000: 8 LEDs (write), a console port (0xffff0004, write a byte), an instruction counter (0xffff000c) and 8 switches you can flip (0xffff0010, read).
Encoding breaks the selected instruction (click any row) into its fields — opcode, rd, funct3, rs1, rs2, funct7 and the immediate pieces — bit by bit, for each of the six formats R, I, S, B, U and J, with what the immediate works out to and the bytes as they sit in memory.
Pipeline draws the instructions that actually ran going through a classic five-stage pipeline (IF ID EX MEM WB), forty at a time: stall cycles, which forwarding path supplied each operand, and the two instructions flushed after every taken branch or jump, with the cycle count and CPI. Turn forwarding off to see how much it saves. Branches resolve in EX with predict-not-taken; it is the textbook model, not any particular chip.
Memory shows the data segment, the stack around sp (watch the frames appear in the recursive factorial) and the code, with the bytes of the last store highlighted.

The examples: a sum loop, recursive factorial with stack frames, bubble sort, string length and reverse, Fibonacci on the LEDs, the calling convention (which registers survive a call and why), the memory-mapped devices, and a short program built to show each pipeline hazard.

The source is kept in this browser; the share link carries it, so a link opens your program as it is.

What is supported

RV32I and M: every instruction except the CSR ones, fence.i and wfi. No compressed instructions, no floating point.
Pseudo-instructions: nop li la mv not neg seqz snez sltz sgtz j jr jal label jalr rs ret call tail beqz bnez blez bgez bltz bgtz bgt ble bgtu bleu and lw rd, label.
Directives: .text .data .word .half .byte .ascii .asciz .string .space .align .equ .globl. Expressions with + - * / % << >> & | ^ ~, character constants, %hi() and %lo(), and GNU numeric local labels (1: with 1b / 1f).
The memory layout is RARS’s: code at 0x00400000, data at 0x10010000, sp from 0x7fffeffc.

The encodings were checked against LLVM’s assembler (llvm-mc) for every instruction and a spread of operands. For other processors there are the 68000 assembler and the 6502 assembler.

Browser support

Any current browser, desktop or phone.

Privacy

Nothing leaves the browser. The program is saved in this browser’s local storage so it is still there next time; nothing is downloaded from anywhere else.