PCB stackup and impedance

Stackup — load a typical stackup and edit it to match your fab’s sheet: thickness (copper in ounces), dielectric εr, and which copper layers are reference planes. The cross-section is drawn not to scale so thin copper stays visible; the total is the finished board thickness.

Impedance — pick a copper layer of the stackup (or enter dimensions by hand). An outer layer over a plane is a microstrip; a layer between two planes is a stripline. Results include Z₀ (or Zdiff), εeff, delay per mm, and capacitance and inductance per mm, and Design for a target solves the width.

Field solver check computes the cross-section’s electrostatic field directly: a finite-volume Laplace solver on a graded mesh with grid lines on every edge, run with and without the dielectric (Z₀ = 1 / (c·√(C·C_air))), on two mesh sizes and extrapolated. It agrees with the classic closed forms below to about 0.3% where they are exact, and is the better answer for coupled pairs, off-centre striplines, and solder mask, where the closed forms are approximations.

Interface widths — width and gap on every signal layer for common targets: 50 Ω RF, USB 90 Ω, Ethernet/HDMI/LVDS 100 Ω, PCIe 85 Ω, DDR 40 Ω.

Delay & skew — flight time, the length mismatch a skew budget allows, the critical length above which a trace needs controlled impedance (delay longer than a sixth of the rise time), and the unit interval of a bit rate in millimetres of trace.