Chris Collins

Tools · electronics

Transistor amplifier designer

Design a transistor amplifier stage from a supply, gain, load, source impedance and bandwidth — common emitter, follower, common base, cascode, long-tailed pair, CE + follower, MOSFET common source / follower / gate, and a class B/AB push-pull stage — with the bias network in standard values, the Q point and its spread with β and temperature, the hybrid-π model, gain and impedances, capacitor sizing, Miller and both corners, swing and THD, every formula worked with numbers, and the circuit checked against circuit-sim's solver.

Added

Works with

How to use it

Pick a topology, a device and the specification; the designer sizes every part, rounds it to E12 or E24, analyses the result as a textbook would — and then solves the same circuit in circuit-sim's engine right here, so every prediction sits next to a simulated number. Examples loads worked designs: a Sedra & Smith style common emitter, an audio preamp, a line driver, a wideband cascode, a long-tailed pair, MOSFET stages and a push-pull output stage in class B (with its crossover notch) and class AB.

How to use it

  1. Choose the topology and the device. BJTs come with their β range (2N3904, BC547B, 2N2222A, BD139 for output stages, and a β = 100, VA = 100 V textbook part); MOSFETs as square-law fits (2N7000, BS170, and a textbook NMOS).

  2. Enter the supply (± for the long-tailed pair and the push-pull stage), the target gain (the magnitude of vout/vin at the amplifier’s input), the load, the source impedance, the low corner the coupling capacitors must reach, the bandwidth you want, and the bias current.

  3. For the gain stages, choose how the emitter (source) resistor is used: fully bypassed gives the most gain (gm·RC) but the least stable one; partly bypassed splits it into an unbypassed RE1 that sets the gain and a bypassed RE2 that only sets the bias; unbypassed lets the whole RE set the gain.

  4. Read the summary: the Q point, gains, input and output resistance, both corners, the largest symmetrical swing and the THD — each with circuit-sim’s number beneath it.

  5. The tabs hold the detail: Parts (calculated against standard values), Q point (load lines and the β / Vth and temperature spread), Small signal (the hybrid-π model drawn with its values, textbook formula against the full network), Frequency (Bode plot with circuit-sim’s AC sweep over it, and the capacitor and time-constant tables), Swing & THD (waveform and harmonics from a circuit-sim transient; the transfer curve for the push-pull stage), Working (the whole design step by step, every formula with its numbers), vs circuit-sim and Explainers.

  6. Open in circuit-sim opens the circuit there — probes on the input, the base or gate, the collector or drain and the output, the AC sweep from the source to the output, and a transient at the THD test level — to change parts, scope it on the instrument bench, or listen to it. SPICE netlist exports it for ngspice or LTspice.

How it designs

  • Bias. The emitter (or source) voltage is set to about a tenth of the supply (at least about 0.5 V) so that VBE’s −2 mV/°C drift is a small fraction of it. The collector (drain) resistor is chosen for the largest symmetrical swing: the output can rise by IC·(RC‖RL) before the transistor cuts off and fall by (VCE − VCE(sat))·Rac/(Rac + RE1) before it saturates, and RC makes the two equal. The base divider follows the stiff-divider rule RTh ≤ (βmin + 1)·RE/10, so the worst-case base current moves the base voltage by under ten per cent; VTh is raised by IB·RTh to compensate. The gain sets the unbypassed RE1 = (RC‖RL)/|Av| − re. MOSFET gates draw no current, so their divider is set to about 1 MΩ for the input resistance.

  • DC. The Q point is solved with the standard values: Thevenin source, VBE = VT·ln(IC/IS) iterated with the device’s IS, square law with channel-length modulation for MOSFETs. The spread table moves β to the datasheet’s limits (Vth for MOSFETs), and the temperature from 0 to 85 °C with SPICE’s laws — IS ∝ T³·exp(−EG/kT) with EG = 1.11 eV, β ∝ T^1.5, Vth −2 mV/°C, Kp ∝ T^−1.5.

  • Small signal. Each transistor becomes its hybrid-π model — gm = IC/VT, rπ = β/gm, ro = VA/IC, Cπ = Cje + gm·τF, Cμ (for MOSFETs gm = 2ID/Vov, ro = 1/λID, Cgs, Cgd) — and the whole circuit, bias resistors, source and load included, is solved as a complex nodal network. Gain, input and output resistance come from it directly, next to the textbook formula.

  • Corners. Coupling and bypass capacitors are sized by short-circuit time constants: each sees a resistance R with the others shorted; the bypass capacitor (which sees the smallest R) takes 80 % of the low corner and the coupling capacitors share the rest, and values are rounded up. The high corner uses open-circuit time constants, fH ≈ 1/(2π ΣRᵢCᵢ), alongside the Miller estimate Cin = Cπ + Cμ(1 + gm·R′L) and the exact −3 dB points from the full network.

  • Large signal. The swing comes from the load lines. The distortion estimate inverts the exponential (or square) law in a power series with the local feedback T = gm·RE1 + R′sig/rπ — HD2 ≈ m/(4(1 + T)) for a BJT, where m = îc/IC is how hard the collector current is modulated — and circuit-sim measures it from a transient (a DFT of two settled cycles). Crossover distortion of the class-B stage cannot be written as a power series, so it is measured only.

The device data are typical figures from the datasheets and vendor SPICE models, rounded; real parts spread widely (that is what the β and Vth rows are for). circuit-sim’s transistors have no Early effect, so its numbers are compared with the prediction without ro; its device capacitances are the dashed capacitors on the schematic, fixed at their values at this bias.

To see a single transistor’s characteristics — the output curves this designer draws its load lines on — use the curve tracer.

Sources: A. S. Sedra and K. C. Smith, Microelectronic Circuits (biasing, hybrid-π, the open- and short-circuit time-constant methods); P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (distortion of degenerated stages, the cascode, the differential pair); P. Horowitz and W. Hill, The Art of Electronics (bootstrapping, push-pull output stages and their bias); ON Semiconductor, NXP and Diodes Inc. datasheets and SPICE models for the 2N3904, BC547B, 2N2222A, BD139/BD140, 2N3906, 2N7000 and BS170.

Sharing

Share link copies a URL that opens this tool with your current settings — every value it remembers between visits, packed into ?s=. Opening a link replaces your saved settings for this tool.

Runs entirely in your browser; nothing you type leaves this page.