Curve tracer and load lines

Diode. I = Is·(expV − I·Rs)/(n·Vt − 1), Vt = kT/q. With a series resistance the equation is implicit; the tool solves it for the junction voltage with a bracketed root finder (the residual rises monotonically, so it always converges). Is scales with temperature as SPICE does, Is(T) = Is·(T/Tnom)^(XTI/n)·expT/Tnom − 1)·EG/(n·Vt, which gives silicon’s familiar −2 mV/°C. Zeners add a breakdown current IBV·exp(−(V + BV)/(NBV·Vt)) with BV(T) = BV·(1 + TBV1·ΔT), plus a reverse-only bulk resistance so the knee can be sharp while the impedance at the test current matches the datasheet’s ZZT. The LED models are fitted to a typical V_F at 20 mA; their EG is a fit parameter that reproduces the datasheet’s V_F temperature coefficient, not the band gap.

BJT. A Gummel–Poon-style transport model without the ohmic resistances and charge storage: the transport current Is·(exp(Vbe/(NF·Vt)) − exp(Vbc/(NR·Vt))) divided by the base charge qb = q1/2·(1 + √(1 + 4·q2)), where q1 = 1/(1 − Vbc/VAF − Vbe/VAR) is the Early effect and q2 the high injection set by IKF; the base current adds the ideal terms Is/BF and Is/BR and the recombination terms ISE/NE and ISC/NC. With VAF, IKF = ∞ and ISE = 0 it is exactly the Ebers–Moll model in circuit-sim (the tests check the two against each other). Collector curves are traced the way a curve tracer does it: for each Vce the tool finds the Vbe that draws the stepped base current. The TIP120 is two such transistors with the datasheet’s internal 8 kΩ and 120 Ω resistors, solved node by node. Because the ohmic resistances are left out, power transistors saturate more sharply here than the real part at amperes.

MOSFET and JFET. The square law with channel-length modulation, the same as circuit-sim’s MOSFET: Id = kp/2·(Vgs − Vth)²·(1 + λVds) in saturation and kp·((Vgs − Vth)·Vds − Vds²/2)·(1 + λVds) in the triode region. Power MOSFETs add a series drain resistance RD (which sets the Rds(on) floor) and an optional mobility reduction THETA. Vth falls 2 mV/°C and kp as (T/Tnom)^−1.5. A JFET is the same law with Vth = VTO < 0 and kp = 2·BETA (SPICE’s NJF), so IDSS = BETA·VTO².

Sources. Where a part has a SPICE model in wide circulation — the Fairchild/onsemi 2N3904 and 2N3906, the Philips/NXP BC547B, the 2N2222 model circuit-sim already uses, the LTspice library’s 1N4148 and 1N5819, the common 1N4007 and 2N5457 models — the tool uses it and says so in the device note. The rest (LEDs, Zeners, BD139, TIP120, the MOSFETs, J201) are fitted here to the typical figures in their datasheets, and the note says which figures. Typical is not guaranteed: the spread between parts of the same number (hFE 100–300, Vth 1–3 V) is far larger than any model error, which is why the fitting tab exists.

With the emitter resistor carrying Ic + Ib, the DC load line is Vcc = Vce + Ic·Rc + (Ic + Ib)·Re; the Q point is where it meets the curve for the bias drive. A divider bias is solved self-consistently — the base current, Vbe and the emitter voltage all depend on each other — by finding the base current that closes the loop V_th = Ib·R_th + Vbe + (Ic + Ib)·Re. For a FET there is no gate current, so Vgs = V_G − Id·Rs.

For signals the emitter (source) resistor is taken as bypassed and the load as capacitor-coupled, so the AC load line has slope −1/r_ac with r_ac = Rc ‖ RL. From Q the output can rise by Iq·r_ac before the transistor cuts off and fall by Vq − V_sat before it saturates; the largest symmetrical swing is twice the smaller, and it is largest when Ic = (Vcc − V_sat)/(R_dc + r_ac). The sine animation runs the instantaneous drive through the real curves and the AC load line at each step, so the distortion you see before hard clipping — the uneven gain of an exponential device — is the model’s, not a sketch’s.

The power hyperbola is Ic·Vce = Pmax. For small parts Pmax is the 25 °C free-air rating; for the BD139, TIP120 and the power MOSFETs it is the rating at a 25 °C case, which needs a large heatsink — derate it (the thermal tool works out by how much). Real SOA curves also have a second-breakdown limit for BJTs at high voltage that this tool does not draw.

The fits are least squares, and each starts from an exact linear version of the problem:

The tests generate data from known parameters, add noise, and check the fits recover them.

Two PWM pins at 31 kHz, each through 10 kΩ and 10 µF and an op-amp follower (LM358 or MCP6002), give two slow, stiff voltage sources. One drives the device through a 100 Ω sense resistor; analogue inputs on both ends of the resistor give the current (I = (A0 − A1)/R_S) and the device voltage (A1). The other feeds a transistor’s base through 100 kΩ (Ib = (A2 − A3)/R_B) or a MOSFET’s gate directly. Measure your 5 V rail and the resistors and put the values in the sketch; the readings are averaged sixteen times per point. It is limited to 0–5 V and tens of milliamps, which covers small-signal diodes, LEDs, small transistors and logic-level MOSFETs at low current — enough to measure your own part’s β, threshold or ideality and design with it rather than with the datasheet’s typical.

The semiconductors tool explains the physics behind these curves — junctions, carriers, band gaps — and the amplifier designer takes a biased stage further, into gain, impedances and frequency response.

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