Chris Collins

Tools · electronics

How a chip is made

A 3-D walk through a chip fab: quartz to a polished wafer with an animated Czochralski pull, a CMOS inverter built up layer by layer (clean, oxidation, resist, exposure, etch, STI, implants, gate, spacers, silicide, contacts), damascene copper and an exploded M1–M6 stack, a k₁·λ/NA lithography calculator with SADP/SAQP and EUV, planar vs FinFET vs GAA, test and packaging from DIP to HBM on an interposer, and a sourced Moore's-law timeline.

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How to use it

The whole journey of a chip, as a set of 3-D models you can turn, slice open, pull apart and step through. It starts with quartz and carbon in an arc furnace and ends with a tested part in a package; in between, the middle tab builds the simplest CMOS circuit — an inverter, one NMOS and one PMOS transistor — one process step at a time, with each step animated (the resist spinning on, light coming through the mask, a plasma etch, an ion beam scanning across) and a short explanation of what happens and why it is done that way.

The models are schematic — a real gate oxide is a thousand times thinner than the well under it — but the order of the steps, the materials, the chemistry and the numbers are the ones in the textbooks and the industry’s published figures.

How to use it

  1. Pick a tab along the top: Sand to wafer, Front end, Back end, Lithography, Transistors, Test & packaging, Timeline or Sources.

  2. In a 3-D view, drag to orbit, scroll or pinch to zoom and right-drag (two fingers) to pan; Reset view brings the camera back. The Cutaway slider slices the model from the front, so you see the classic cross-section; the Exploded slider pulls the layers apart vertically.

  3. Step through with Next and Prev or the numbered dots, or press Play the steps. Moving forward one step plays its animation (Replay plays it again): new films grow up from the surface, etched and stripped layers fade away. The step card says what happens, why, and keeps count of the masks used so far.

  4. Click or tap any part of the model, its label or its name in the list for an information card: what it is, what it is made of, and the step at which it was added and removed.

  5. Some steps carry a small calculator: the spin speed and resist thickness, the wet against dry etch profile, and the implant’s dose and energy (projected range, straggle and peak concentration, with the profile plotted).

  6. Sand to wafer ends with a table of wafer sizes from 100 mm to the abandoned 450 mm, with the dies per wafer for a die area you choose, a wafer map, and a link that opens the same numbers in the chip-yield tool.

  7. Back end has two views: the dual-damascene copper steps, and an exploded stack of six metal levels with their vias. Test & packaging has the assembly flow step by step and a gallery of packages — DIP, QFP, wire-bond BGA, flip-chip BGA, a GPU with four HBM stacks on a silicon interposer, and a 3-D hybrid-bonded stack.

  8. In Lithography, choose a light source from g-line to high-NA EUV, or set λ, NA and k₁ yourself, and enter a pitch to see how many exposures it would take. Step through LELE, SADP and SAQP, and see why EUV loses most of its light in its mirrors.

  9. The Timeline plots the transistor counts of real chips from the 4004 to the B200 and the wafer-scale Cerebras WSE-3 on a log scale, with Moore’s two-year doubling and a fitted line; hover or tap a point for the chip and its source.

To see how the NMOS and PMOS built in the front end make an inverter — and NAND and NOR gates and their layouts — try the CMOS gate designer. For the physics of the devices, see the semiconductor explorer.

The method

  • Process flow. The front end follows a textbook twin-well CMOS flow with shallow trench isolation (Plummer, Deal & Griffin, Silicon VLSI Technology, chapter 2): pad oxide and nitride, the STI mask, trench etch, fill and CMP; n-well and p-well masks and implants, anneal; gate oxide, polysilicon and the gate mask; LDD implants, nitride spacers, source/drain implants and a spike anneal; nickel salicide; the pre-metal dielectric; contacts and tungsten plugs. Modern processes add high-k metal gates, strained channels, epitaxial source/drain and FinFETs or nanosheets — the Transistors tab shows those.

  • Lithography. Resolution (half-pitch) CD = k₁·λ/NA and depth of focus DOF = k₂·λ/NA² (the Rayleigh criteria). A single exposure cannot go below k₁ = 0.25 for lines and spaces; the number of exposures for a target pitch is the smallest whole number that brings the per-exposure pitch above that limit. The preset NA and k₁ values are typical production values, chosen so that the EUV presets match ASML’s quoted 13 nm (NXE, NA 0.33) and 8 nm (EXE, NA 0.55).

  • Multiple patterning. The diagrams are computed: SADP puts a spacer of width s on both sides of each mandrel of width w at pitch P; with P = 2(w + s) the spacers fall at exactly P/2. SAQP repeats that on the first spacers to reach P/4.

  • Implants. Projected range and straggle are interpolated (log–log) from the standard LSS range tables for boron, phosphorus and arsenic in amorphous silicon, as reproduced in Plummer et al. The profile is a Gaussian with peak dose/(√(2π)·ΔRp) — no channelling tails or diffusion.

  • Dies per wafer uses exactly the same grid count as chip-yield (whole dies inside the usable circle, trying sixteen grid offsets), with 3 mm edge exclusion and a 0.1 mm scribe.

  • EUV optics. Transmission through n mirrors of reflectivity R is Rn; about 70% per Mo/Si multilayer mirror and about ten reflections are the commonly quoted round numbers.

  • Node names. The table gives the contacted gate pitch and minimum metal pitch from the companies' IEDM/VLSI papers as collected by WikiChip, and the IRDS roadmap’s ground rules, rounded. Treat them as approximate.

  • Timeline. Transistor counts are as published by the makers (mostly via Wikipedia’s transistor-count list, vendor pages for the newest), each with its source. The fitted line is a least-squares fit of log₂(count) against year over the single- and multi-die chips; the wafer-scale parts are plotted but excluded.

Limits

  • The 3-D models are schematic and not to scale; the package gallery is in millimetres at typical sizes, but with far fewer bumps, balls and wires than a real part.

  • Many steps are left out or merged: most cleans, metrology and inspection, the sacrificial oxide, well-tie and threshold-adjust implants, the contact-etch-stop stress liner, and every step of modern FinFET and nanosheet flows.

  • Energy per kilogram, tool prices and the EUV source figures are approximate public figures.

Sources

The page loads three.js 0.147.0 (MIT licence) from cdn.jsdelivr.net the first time a 3-D tab opens. Nothing is sent anywhere; your place in each step-through and the slider settings stay in this browser’s local storage.

Runs entirely in your browser — network requests go only to the services named on this page.