Chris Collins

Tools · electronics

CMOS gate designer

Type a Boolean expression and get the static CMOS gate — pull-down and dual pull-up networks drawn, sized and checked switch by switch against the truth table — then size a path by logical effort, explore the inverter's transfer curve, noise margins and power, and lay the gate out on a λ grid along its Euler path with live SCMOS-style design rule checks.

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How to use it

How a logic gate is built from transistors, from the expression down to the mask layout. Type a Boolean expression such as !(A&(B|C)) and the tool builds the static CMOS gate: the NMOS pull-down network (AND in series, OR in parallel) between the output and ground, and its dual PMOS pull-up (series and parallel swapped) between the supply and the output. It draws the transistor schematic, evaluates the networks switch by switch for every input combination, and shows which transistors conduct and carry the output’s value. Then it sizes the gate, times a path of gates by the method of logical effort, plots the inverter’s transfer curve, works out power, and lays the gate out on a λ grid with the transistors ordered along an Euler path, checking it against design rules as you edit.

How to use it

  1. Expression → transistors. Pick a preset (INV, NAND2/3, NOR2/3, AOI21, AOI22, OAI21, AND2, XOR, the transmission-gate XOR and MUX2, and the 28-transistor mirror full adder) or type an expression. NOT is !, ~, ¬ or a trailing '; AND is &, *, · or just writing AB; OR is | or +; XOR is ^. The words AND, OR, NOT, XOR, NAND, NOR and XNOR work too.

  2. Click an input, or a row of the truth table, to see that combination on the schematic: transistors carrying the output’s value are orange, other transistors that are on are green. The table checks the switch network against the expression for every row and says which network conducts.

  3. A non-inverting function (AND, OR, XOR, a mux) gets an output inverter or inverted inputs, whichever needs fewer transistors; Construction lets you force either. The γ field is the mobility ratio μn/μp that sets how much wider the PMOS transistors are.

  4. Open in circuit-sim takes the transistor netlist to the circuit simulator with a pulse source on each input (periods doubling, so the transient walks the whole truth table), a load capacitor and probes, to watch the gate switch. Download SPICE netlist gives the same circuit for ngspice.

  5. Sizing & logical effort lists each input’s logical effort g and the gate’s parasitic delay p, computed from the sized transistors, beside the textbook table. Below it, build a path of gates with branching, an input capacitance and a load: it gives the path effort F = GBH, the best stage effort, each gate’s input capacitance, the delay in τ and in picoseconds for a chosen process, and how many inverters to add for the fastest path.

  6. Inverter, power, ring oscillator plots the voltage transfer characteristic for the square-law or alpha-power model, with Vm, VIL/VIH, the noise margins and the gain at Vm, and the curve for a quarter and four times the β ratio. Power gives dynamic, short-circuit and subthreshold leakage power, leakage against threshold at three temperatures, and an illustrative leakage share across nodes from 180 nm to 7 nm. The ring oscillator estimates frequency from the stage count and node.

  7. Layout & DRC lays out a complementary stage: the Euler path found (the gate order and the nodes along each diffusion strip), the generated layout, and a small editor — draw n-well, diffusion, poly, contacts, metal1, vias and metal2 on the λ grid, select and drag, delete, undo — with every design rule re-checked and violations outlined. Stick diagram draws the same shapes as lines. Export as SVG or as CIF with the SCMOS layer names.

The method

Synthesis. The expression is parsed, pushed into negation normal form (XOR expanded to a sum of products), and turned into a series-parallel tree. A single complementary stage computes F = ¬G, where G is the pull-down function, so the tool tries both G = ¬F (one stage, with inverters for complemented inputs) and G = F (a gate for ¬F and an output inverter) and keeps the one with fewer transistors. The pull-up is the dual tree. No Boolean minimisation is done — for that, minimise the expression in the Boolean logic tool first.

Switch-level simulation. Each transistor is a switch, NMOS closed when its gate is 1 and PMOS when it is 0. Nets joined by closed switches take the value of whatever drives them — VDD, GND or an input (for transmission gates) — or X if two values meet, or Z if nothing does; the stages are iterated until nothing changes. A correct static gate never produces X or Z.

Sizing and logical effort (Sutherland, Sproull and Harris, Logical Effort, 1999; Weste and Harris, CMOS VLSI Design, 4th ed., ch. 4). Every network is sized so its weakest path matches the reference inverter (NMOS width 1, PMOS width γ): series transistors share the resistance in proportion to their depth, parallel ones each get the full width. An input’s logical effort is the width it drives ÷ (1 + γ) — 4/3 for a NAND2 and 5/3 for a NOR2 at γ = 2 — and the parasitic delay is the diffusion width on the output ÷ (1 + γ), with the narrowest end of each series chain placed on the output. A path’s delay is D = N·F1/N + P in units of τ, minimised when every stage bears the same effort; the best stage effort for pinv = 1 is ρ ≈ 3.59, and τ ≈ FO4/5. The FO4 delays per node are rough approximations (about 70 ps at 180 nm down to about 5 ps at 7 nm) and are labelled as such.

The inverter. Long-channel square law with channel-length modulation, or the alpha-power law (Sakurai and Newton, 1990) for velocity-saturated short channels, with a small subthreshold tail. Vout is solved for each Vin by equating the NMOS and PMOS currents. The switching threshold is Vm = (Vtn + r(VDD − |Vtp|)) / (1 + r), r = (βp/βn)1/α; VIL and VIH are where the slope is −1. For the symmetric square-law inverter VIL = (3VDD + 2Vt)/8, a check the tests make.

Power. Dynamic power αCV²f; short-circuit power from Veendrick (1984), (β/12)(VDD − 2Vt)³·τin·f; subthreshold leakage I0·10−Vth/S with the swing S growing with absolute temperature and Vth falling about 1 mV/K. The node comparison is illustrative: rough high-performance Ioff figures and supply voltages, not any foundry’s data.

Layout. The transistors of a stage are the edges of two graphs (NMOS and PMOS) whose vertices are nets. Searching for trails through both graphs with the same gate sequence (Uehara and vanCleemput, 1981), allowing the fewest diffusion breaks, gives the order of the poly columns so each network is one strip of shared diffusion. The generated cell puts the p-strip in an n-well under the VDD rail and the n-strip over the GND rail, contacts where a node meets a rail, the output or a repeated internal node, and runs the output and repeated nodes on metal2 tracks. The design rules are a simplified subset of the MOSIS SCMOS rules (revision 8) in λ, with the 1.5λ contact surrounds rounded up to 2λ; width, spacing, gate extensions, contact and via enclosure, contact-to-gate spacing and well rules are checked. The area in µm² takes λ = half the node, which held only down to about 130 nm.

circuit-sim. The netlist opens with circuit-sim’s square-law MOSFETs (threshold 1 V, Kp scaled by each transistor’s width, μn/μp = 2) at VDD = 5 V and a 50 fF load per output; the tests run the transient for every preset and check the output against the truth table.

Not modelled: dynamic logic (domino, precharge), ratioed logic, the 6-transistor XOR, body effect in the switch view, wire capacitance and resistance, and process variation.

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