Data converters lab

How analogue becomes digital and back, one idea at a time, with every waveform live. Each tab is a small lab: move a slider and the time-domain picture, the spectrum and the numbers all follow. The sigma-delta tab and the wagon wheel animate; the SAR converter steps through its binary search one comparison at a time.

This is the "how it works" companion to the ADC accuracy calculator, which does the error budget for a real design. (The sampling and simulation tool is about statistical sampling, not signals.)

How to use it

Sampling & aliasing. Set the sample rate and drag the signal frequency, or press Sweep to run it from 0 to 2.5 fs. Above fs/2 the samples (orange) also fit a lower sine — the red dashed alias. The spectrum shows the input’s images at k·fs ± f and which one lands in the first Nyquist zone; the folding diagram plots the alias against the input (a triangle wave: even zones come back mirrored). The wagon wheel shows the same thing as a camera sees it: try Stands still, Backwards and Creeps forward, and mark one spoke to see the true rotation. The anti-alias panel gives the Butterworth order needed to reach the converter’s noise floor at fs − fpass, and a table of how it collapses as the sample rate rises.
Quantisation. The bits slider (1–16) redraws the staircase, the error waveform (always within ±½ LSB) and the spectrum of the quantised sine. Compare the measured SNR with 6.02N + 1.76 dB — the derivation is worked out below the plot for the chosen N — and lower the level to see the SNR fall dB for dB. Switch dither between none, RPDF and TPDF: the harmonics (distortion that follows the signal) dissolve into a flat noise floor. Listen plays a quantised 440 Hz tone at a few bits through WebAudio, with and without dither, and a fade-out where undithered audio breaks up and vanishes while dithered audio stays clean under the hiss. Turn the volume down first. Oversampling and averaging simulates a noisy ADC averaged in blocks of OSR samples, against the 10·log₁₀(OSR) dB theory — and shows the gain disappear when there is too little noise.
SAR. Choose an input, the resolution and the reference, then Step or Play: each step tries one bit, the comparator keeps it or clears it, and the search interval halves. The capacitor array shows which bottom plates are switched to Vref, and the comparator’s input Vx = Vdac − Vin.
Flash. Two to five bits: the resistor ladder, a comparator per threshold, the thermometer code, and the encoder. Flip a comparator injects a "bubble" and shows why a top-most-one encoder jumps while counting ones does not.
Sigma-delta. Run a first- or second-order modulator clock by clock: the integrator values, the ±1 bitstream, and its running average converging on the input. The noise-shaping plot shows the bitstream’s spectrum against the noise transfer functions (20 and 40 dB/decade) and the in-band SQNR for the chosen OSR; the decimation plot recovers a slow input with a sinc^L+1 filter; the last plot is ENOB against OSR, theory and measurement.
Dual-slope & pipeline. The integrating converter’s timing diagram, with ghosts at ¼, ½, ¾ and full scale, the counts, and the normal-mode rejection of 50 and 60 Hz for the chosen integration time. The pipeline panel resolves 1.5 bits per stage and shows digital correction absorbing a comparator offset.
R-2R & binary DACs. Toggle the bits of an R-2R ladder and read every node voltage and leg current; add resistor mismatch to see the transfer bend and the DNL (worst at the MSB step). The binary-weighted DAC shows the resistor spread and the tolerance the MSB resistor would need.
PWM & ΔΣ DACs. Give the timer clock, resolution and RC (or pick an Arduino, RP2040 or ESP32 preset): the tool gives the PWM frequency, the exact ripple, the settling time and the RC that keeps ripple under ½ LSB, plus a plot of how ripple and settling trade against resolution. The second panel runs PWM and a first-order delta-sigma bitstream with the same code through the same RC.
INL / DNL. Simulate a non-ideal ADC (random threshold errors, a bow, RP2040-style DNL spikes) and measure it with a ramp histogram test, or a mismatched R-2R DAC; see DNL, INL, missing codes and non-monotonic steps.
MCU ADCs. A table of common microcontroller ADCs, the ESP32’s non-linearity (an illustrative model) with raw, two-point and curve-fit calibration, a sample-and-hold settling calculator with presets, and a guide to choosing the reference.

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The maths

Aliasing. A tone f sampled at fs appears at |f − fs·round(f/fs)|, in Nyquist zone ⌊2f/fs⌋ + 1; even zones are mirrored. A wheel with s identical spokes at r rev/s filmed at F frames/s appears to turn at alias(r·s, F)/s, signed — negative is backwards.
Anti-alias filter. Energy at fs − f folds onto f, so the filter must reach the target attenuation A (here 6.02N + 1.76 dB) at fs − fpass. A Butterworth with its corner at fpass needs order n = log₁₀(10^A/10 − 1) / (2·log₁₀fs − fpass)/fpass.
Quantisation. An N-bit mid-rise quantiser over ±1 has q = 2/2^N. For an input that is busy enough, the error is uniform on ±q/2 with power q²/12; a full-scale sine has power ½, so SNR = 1.5·4^N = 6.02N + 1.76 dB. The tests check the measured value is within 0.5 dB of this from 6 to 16 bits. RPDF dither (uniform ±½ LSB) doubles the noise power; TPDF (two summed, triangular ±1 LSB) triples it (+4.8 dB) and makes the error’s mean and variance independent of the signal — the standard choice for audio (Lipshitz, Wannamaker and Vanderkooy, "Quantization and dither: a theoretical survey", JAES 1992).
Oversampling. Averaging OSR samples with independent noise divides the noise power by OSR: 10·log₁₀(OSR) dB, half a bit per doubling (Atmel AVR121, Silicon Labs AN118).
SAR. N comparisons, MSB first: keep bit i if Vin ≥ Vref·(code with bit i set)/2^N. The result is ⌊Vin/Vref·2^N⌋.
Sigma-delta. First order: u += x − y, y = sign(u), so Y = X + (1 − z⁻¹)E. Second order (two integrators, both fed back): Y = X + (1 − z⁻¹)²E. The ideal SQNR of an order-L loop with a B-bit quantiser is 6.02B + 1.76 − 10·log₁₀(π^2L/(2L + 1)) + (20L + 10)·log₁₀(OSR) (Schreier and Temes, Understanding Delta-Sigma Data Converters). The measured points come from a −6 dBFS tone, a 16 384-point Blackman–Harris FFT and the noise power summed to fs/(2·OSR).
Dual slope. n2 = n1·Vin/Vref, independent of R, C and the clock; integrating for T rejects a frequency f by |sin(πfT)/(πfT)|, with nulls at every multiple of 1/T.
Pipeline. Each 1.5-bit stage decides d ∈ {−1, 0, +1} with comparators at ±Vref/4 and passes on 2v − d·Vref; the input is Σ d_k·Vref/2^k plus the last residue.
R-2R ladder. Solved by nodal analysis, so resistor errors are exact rather than approximated. Unloaded, Vout = Vref·code/2^N and the output resistance is R for every code.
PWM. One RC filter’s steady-state peak-to-peak ripple for duty D, period T and time constant τ is Vref·(1 − e^−DT/τ)(1 − e^{−(1−D)T/τ})/(1 − e^−T/τ), worst at 50 %, where it is Vref·tanh(T/4τ). Settling to ½ LSB takes τ·ln 2^N+1. The two-stage figures use the fundamental only.
INL and DNL. The ADC is simulated as its transition levels and measured with a code-density (histogram) test, as in IEEE Std 1241: DNL = hits/mean − 1, INL the end-point-corrected running sum, DNL = −1 a missing code.
Sample and hold. A full-scale step on C_s through R_source + R_switch settles to ½ LSB in (R_s + R_sw)·C_s·ln 2^N+1; a pin capacitor C_ext drops by C_s/(C_s + C_ext) when the switch closes.

Assumptions and sources

The ESP32 curve is an illustrative model with the shape of published measurements (a dead zone near 0 V, compression towards full scale, a chip-to-chip reference spread around 1100 mV), not Espressif data. The recommended input ranges per attenuation are from the ESP-IDF ADC documentation. Use the calibrated API on a real chip.
The microcontroller table gives typical datasheet figures (ATmega328P, STM32F103, STM32G4, STM32H743, RP2040 including erratum RP2040-E11, ESP32, SAMD21, nRF52840). They vary with package, clock and supply; check the datasheet for your part.
The quantiser is ideal apart from what you add; the modulators are ideal discrete-time loops (no integrator leakage, no comparator offset); the R-2R ladder’s switches are ideal and its output unloaded.

For the error budget of a real ADC design see ADC accuracy; for measuring a converter’s output spectrum see the spectrum analyser; for the filters around a converter see the digital filter designer.

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Works with

How to use it

The maths

Assumptions and sources

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