FPGA calculators

Setup/hold: enter the clock period and the path’s delays (from nextpnr’s or Vivado’s timing report, or a data sheet) to get setup and hold slack, the path’s fmax, and a timing diagram that shows where the data changes relative to the setup and hold windows.

CDC & MTBF: the mean time between synchroniser failures, MTBF = e^(t_r/τ) / (T₀ · f_clk · f_data), for one to four flip-flops (Ginosar, "Metastability and Synchronizers: A Tutorial", IEEE Design & Test, 2011) — and Verilog for the four crossing patterns: a two-flop synchroniser, a pulse synchroniser, a req/ack handshake for words, and an asynchronous FIFO with Gray-code pointers (after Cummings, SNUG 2002). The default τ and T₀ are illustrative only; use your vendor’s figures (Xilinx XAPP094/WP272, Intel WP-01082) for a real design.

PLL: iCE40 SB_PLL40 (DIVR, DIVF, DIVQ, FILTER_RANGE) and ECP5 EHXPLLL (CLKI_DIV, CLKFB_DIV, CLKOP_DIV, phase) settings for an input and wanted output frequency, with the instantiation. The searches are ports of icepll (Project IceStorm) and ecppll (Project Trellis) — the ECP5 one including its single-precision arithmetic — and are tested against those tools' output for over 160 frequency pairs.

FIFO depth: how many words are left after a write burst when the reader is slower, with idle cycles on either side, the reader’s reaction time, and a check that the long-term rates balance (method: P. Satish, "Calculation of FIFO Depth – Made Easy").

Video timing: 26 VESA DMT and CTA-861 modes (640×480 to 1080p) with porches, sync widths and polarities, pixel clock and the PLL settings to make it, a line diagram, and a Verilog timing generator. Every mode is checked against the tables in Linux’s drm_edid.c.

UART: the divisor for a baud rate from your clock, the resulting error, and a table of common rates.

BRAM/DSP: block RAMs for a depth × width memory (best aspect ratio) and multiplier blocks for an A × B product on iCE40, ECP5, Xilinx 7-series and Gowin GW1N, with the share of common devices.

CRC/LFSR: Verilog for a parallel CRC — any CRC from the CRC tool's catalogue or your own polynomial — taking any number of data bits per clock; the equations are checked against that tool’s software CRC. And maximal-length LFSRs from 3 to 168 bits with the taps from Xilinx XAPP052.

Pins: pick a board, paste your top module, and assign each port bit to a board pin (or Match by name); get a PCF, LPF, XDC or CST file. Boards: iCEBreaker, iCEstick, TinyFPGA BX, UPduino v3.0, Fomu, ULX3S, OrangeCrab, Colorlight i5, Arty A7, Basys 3, Tang Nano 9K, with pin data extracted from each board’s official constraint files (linked under the table). The FPGA playground uses the same pin maps for its board presets.

Timing is a single-path model; real tools add clock-tree, on-chip variation and input/output delays. MTBF depends heavily on τ, which only the vendor’s characterisation gives.

The PLL tabs cover icepll’s and ecppll’s main modes (not icepll’s crystal search or ecppll’s high-resolution mode); check the result in the vendor’s or nextpnr’s report. Gowin and Xilinx PLLs are not covered.

BRAM and DSP counts are estimates for straightforward inference; synthesis may use LUT RAM, cascade differently or add fabric adders.

The LFSR table leaves out 102 bits: the tap set we had could not be confirmed as maximal length.

Board pin maps cover the common I/O (clocks, LEDs, buttons, switches, UART, Pmods and headers, video, and the configuration flash where the board file lists it), not DRAM, and follow one board revision each; check your revision’s schematic.