Logic analyser
Open VCD, Saleae, or sigrok captures (or raw bytes) in the browser, zoom and measure the waveforms with cursors, and decode UART, I2C, SPI, and 1-Wire traffic into bytes, text, and a searchable event list.
Added · updated 28 October 2026
Works with
- HDL trainer: learn Verilog by doing FPGA and HDLopens the HDL trainer sandbox’s waveform from Open in logic analyser (or its downloaded VCD)
- Digital logic simulator Electronicsopens the timing diagram’s signals from Open in logic analyser (or the downloaded VCD)
- FPGA playground FPGA and HDLopens the simulation’s waveform from Open in logic analyser (or the downloaded VCD)
- Peripheral protocols, simulated IoT and embeddedopens its simulated PS/2, WS2812, IR, DMX, MIDI and Centronics waveforms
- Pico hardware bench IoT and embeddedopens the PIO captures a Raspberry Pi Pico takes there, channels already named
- Bus protocols, simulated IoT and embeddedopens the SPI, I²C, UART, 1-Wire, SD and JTAG transactions generated there
How to use it
Open capture (or drop a file on the page) accepts:
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VCD — from sigrok/PulseView, GTKWave, Verilog/VHDL simulators, or cheap 8-channel analysers. Multi-bit variables are split into one channel per bit.
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Saleae Logic CSV —
Time [s], Channel 0, …, one row per change. -
sigrok CSV — one row per sample; the sample rate comes from the
; Samplerate:comment or the Sample rate box. -
Raw binary (
.bin,.raw) — one byte per sample, bit 0 = channel 0, at the Sample rate.
The Demo capture has a UART "Hello, world!", a BME280 chip-ID read over I2C, a W25Q flash JEDEC-ID read over SPI, and a DS18B20 Skip ROM / Convert T over 1-Wire, already decoded.
The HDL trainer sandbox, the logic simulator and the FPGA playground each have an Open in logic analyser button that opens their waveform here in a new tab, with no file to save; the capture goes through this browser’s local storage and is deleted once it has been read.
Viewing: scroll or pinch to zoom around the pointer, drag (or Shift+scroll) to pan, double-click to fit. Click to drop cursor A and Shift+click for cursor B; clicks snap to the nearest edge. The readout shows Δt and 1/Δt, and Measurements gives each channel’s edge count, frequency, duty cycle, and shortest high and low pulses — for the whole capture or between the cursors. Export VCD converts any loaded capture into VCD for PulseView or GTKWave.
⛶ Full screen (or F) gives the waveforms the whole screen — the browser’s full screen where
it is allowed, otherwise a full-window layer (iPhone). The channel rows grow to use the height
and are redrawn as the window changes; decoders, events and measurements follow below. Escape
leaves.
Decoders (added automatically when channel names such as SCL, MOSI, or TX give them away):
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UART — any baud rate, 5–9 data bits, parity, 1/1.5/2 stop bits, inverted (RS-232 level) lines. Auto measures the shortest pulse — one bit time — and picks the nearest standard rate. Parity and framing errors are marked in red.
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I2C — START, repeated START, STOP, 7-bit address with read/write, data bytes, and ACK/NACK (10-bit addressing is shown as two address bytes).
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SPI — modes 0–3, word sizes from 8 to 32 bits, MSB or LSB first, optional chip select (active low or high); MOSI and MISO decode on separate rows.
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1-Wire — standard-speed resets, presence pulses, and bytes, with ROM and DS18B20 function commands named.
Click a row in Events to jump to it. Decoded data collects the bytes per decoder (and the text for UART) to copy, and Export decoded CSV saves every annotation. Decoding samples each line at the clock edge or bit centre, so the capture should be sampled at least 4–10× faster than the signal. Everything runs locally; files never leave the browser.
Feedback is a gift. Something to improve, a feature to add, or a bug? Tell me.
Runs entirely in your browser; nothing you type leaves this page.