Chris Collins

Tools · fpga

FPGA playground

Write Verilog, simulate it with Icarus Verilog, synthesise with Yosys and build a bitstream for Lattice iCE40, ECP5, CrossLink-NX, MachXO or Gowin FPGAs — or synthesise for Xilinx and Intel and export a Vivado or Quartus project — with the real open-source FPGA tools in your browser, and 44 documented examples.

Added · updated 28 October 2026

Works with

How to use it

The open-source FPGA toolchain, in this page: Icarus Verilog simulates, Yosys synthesises, nextpnr places and routes, and the families' bitstream tools pack the result: icepack (Project IceStorm), ecppack (Project Trellis), prjoxide (Project Oxide) and gowin_pack (Apicula). They are the same programs you would install, compiled to WebAssembly by YoWASP (Icarus by @veriflow/iverilog-wasm; Apicula, which is Python, runs in Pyodide), and they run in Web Workers. Your code never leaves the browser.

How to use it

  1. Open an example (Examples…, 44 of them in eight groups) or start a New project. The About tab shows what the example does, how it works, what to look for in simulation and on the board — it is the comment block at the top of the example’s main Verilog file, so your own designs get one too: start the file with // # Title, // ## Heading lines, // - ` list items, `code and bold.

  2. A project holds several files: Verilog (.v) or SystemVerilog (.sv, the subset Yosys reads), a constraints file, and testbenches. A file named tb_*.v or _tb.v (or a portless module that calls $finish) is a testbench: it is simulated but never synthesised. Projects are kept in this browser (IndexedDB); *Export zip and Import zip move them.

  3. Pick a Target: a board, grouped by vendor and family, or Custom … for any supported device. The badges under it say what that target can do here — Simulate, Synthesise, Place & route, Bitstream — and which tool finishes the job when it is not everything:

    Family Boards Here

    Lattice iCE40

    iCEBreaker, iCEstick, TinyFPGA BX, UPduino v3, Fomu (any LP384–HX8K, UP5K, U4K)

    full flow

    Lattice ECP5

    ULX3S, OrangeCrab, Colorlight i5 (12k–85k, UM, UM5G)

    full flow

    Gowin

    Tang Nano 1K, 4K, 9K, 20K, Tang Primer 20K and 25K (GW1N-1/4/9, GW1NZ-1, GW1NSR-4C, GW1NR-9/9C, GW2A-18/18C, GW5A-25A)

    full flow

    Lattice CrossLink-NX

    CrossLink-NX Evaluation Board (LIFCL-17, LIFCL-40)

    full flow

    Lattice MachXO2/3

    MachXO3LF Starter Kit (MachXO2-640U/1200, MachXO3LF-6900)

    full flow (experimental in nextpnr)

    AMD Xilinx 7-series

    Arty A7, Basys 3, Nexys A7, Cmod A7, Zybo Z7 (Artix-7, Spartan-7, Zynq PL)

    synthesis, then Vivado

    Intel (Altera)

    DE10-Lite, DE0-Nano (MAX 10, Cyclone IV E, Cyclone 10 LP, Cyclone V)

    synthesis, then Quartus

    Top is the module to synthesise; Clock is the frequency nextpnr checks timing against.

  4. ▶ Simulate runs the testbench with Icarus Verilog (-g2012). $display output appears above the waveforms, and the examples print PASS or FAIL. Without a testbench, the design is clocked for 64 cycles with Yosys’s sim pass instead.

  5. Synthesise runs the family’s Yosys flow (synth_ice40, synth_ecp5, synth_gowin, synth_lattice, synth_xilinx, synth_intel, or the generic synth): LUTs, flip-flops, carry cells, block RAM, DSPs and PLLs, the full cell list, and the log.

  6. Place & route runs nextpnr with your constraints (top.pcf for iCE40, top.lpf for ECP5 and MachXO, top.cst for Gowin, top.pdc for CrossLink-NX): the achieved Fmax against your clock, critical paths step by step, the device utilisation, and a floorplan where the format allows.

  7. Build bitstream (Ctrl/⌘+Enter) does all three and packs the result: download top.bin (iCE40), top.bit (ECP5, CrossLink-NX, MachXO) or top.fs (Gowin) and copy the programming command for your board. For Xilinx and Intel targets the button is Export Vivado project or Export Quartus project: it synthesises to check the design, then downloads a zip with the sources, the constraints (top.xdc; or a Quartus .qpf/.qsf with the pins and an .sdc with the clock), a build script (vivado -mode batch -source build.tcl, quartus_sh -t build.tcl), a programming script and a Makefile that runs the testbench with Icarus.

Errors and warnings with a file and line are marked in the editor’s gutter and underlined; click one in the list to jump to it. The Logs tab keeps each tool’s full output.

Portable designs and board.v

Most examples are portable: their top module uses standard port names — clk, led[], btn[], sw[], uart_rx, uart_tx, io[] (a Pmod-style header), seg[]/dp/an[], vga_r/g/b, vga_hs/vga_vs, audio, ws2812, ps2_clk/ps2_data — and a CLK_HZ parameter. For each board the page writes board.v, a board_top module that passes the board’s clock frequency to CLK_HZ, wires each role to the board’s pins and inverts the active-low ones (the Tang Nano LEDs, the Basys 3 seven-segment display), and the constraints for exactly those pins. Pick another board and both are regenerated, so one design runs on an iCEBreaker, a Tang Nano and an Arty. Ports a board lacks are listed at the top of board.v (inputs read 0). Edit the design, not board.v.

Waveforms

Drag to pan, scroll (or ＋/－) to zoom, Fit to see everything. Click to place cursor A, and shift-click (or press B, then click) for cursor B: the readout shows the time between them and the matching frequency. Cursors snap to the nearest edge. Click a bus’s name to cycle its radix (hex, unsigned, signed, binary, ASCII). Tick signals in the list below the waveforms to show them, and use Download VCD to open the trace in GTKWave, Surfer or the logic analyser.

Schematic

The Schematic tab draws the netlist with netlistsvg (laid out by ELK in a Web Worker): RTL is the design after Yosys’s prep -flatten — adders, multiplexers, comparators and flip-flops, before they are mapped to the FPGA’s cells, much like Yosys’s show — and Gate level is the mapped netlist (SB_LUT4, TRELLIS_FF, LUT4/DFF/ALU on Gowin, FDRE/CARRY4 on Xilinx…). Designs over 400 cells are not drawn; pick a sub-module as Top to see part of a big design.

On this tab the schematic takes the full width (◧ Editor puts the editor back beside it) and most of the window’s height; drag the grip under it to make it taller or shorter (remembered). Drag to pan, scroll or pinch to zoom, or use − *, *Fit* and *1:1* (keys `` - 0 1, arrows to pan, / to search). *Map shows a mini-map when the drawing is bigger than the view. Click a cell, port or wire to highlight it and see its name, type and what it connects to (the names in the panel are links); Find searches cells, ports and nets by name or cell type (Enter jumps to the next match). SVG and PNG download the drawing.

⧉ Pop out opens the schematic in its own window — put it on a second screen. It has its own pan, zoom and search, follows every new synthesis on this page (and its RTL / gate-level picker asks this page for the other view), and closes when this page does. If the browser blocks pop-ups, the schematic opens full screen instead; ⛶ Full in the schematic’s toolbar does that any time.

Full screen

⛶ Full screen (or F) gives the editor and the results the whole screen; ◫ Panels shows the project bar again. On the Schematic tab, full screen is all schematic. Esc leaves.

Programming the board

The Bitstream tab lists each board’s programming commands — openFPGALoader for most boards (openFPGALoader -b tangnano9k top.fs, add -f to write the flash), iceprog for the FTDI-based iCE40 boards, dfu-util for the DFU bootloaders of the Fomu and OrangeCrab (after dfu-suffix), tinyprog for the TinyFPGA BX — and the board’s pins with links to the official constraint files they come from. All of them are in the OSS CAD Suite. In Chrome and Edge there is also an experimental Program over WebUSB button using YoWASP’s WebUSB build of openFPGALoader. It has not been tested with hardware here, and it cannot open a device that the operating system’s own driver has claimed (the FTDI driver on macOS, for example), so the downloaded file and the command line are the dependable route.

Examples

Every example has a documentation comment (what it does, how it works, its ports and parameters, what to look for in simulation and on the board, and the boards it has been built for), comments in the code, and a self-checking testbench; the site’s tests simulate every one with Icarus, synthesise it for its listed families and place and route it on its listed boards.

  • Basics: blinky, an up/down counter, a PWM breathing LED, a Knight Rider LED chaser, logic gates and decoders.

  • I/O and user interface: a button debouncer and edge detector, a rotary encoder, a multiplexed 7-segment display, a stopwatch, a reaction-time game, a frequency counter that prints over the UART, servo PWM, a stepper motor driver.

  • Communication: UART echo, UART-controlled LEDs, an SPI master (reading a PmodALS light sensor), an SPI slave register file, an I²C master writing and reading an EEPROM (with an EEPROM model in the testbench), a PS/2 keyboard receiver, a WS2812 RGB LED driver.

  • Video and audio: VGA colour bars, a bouncing ball, an 80 × 30 text terminal with a font ROM, Pong, Conway’s Game of Life with double-buffered block RAM, a DVI/HDMI TMDS encoder, an NCO tone generator with a sigma-delta DAC, and the iCEBreaker VGA example with the iCE40 PLL.

  • Memory: a FIFO in block RAM, an asynchronous (two-clock) FIFO with Gray-code pointers, a dual-port block RAM, and an SDRAM controller sketch tested against an SDRAM model.

  • Arithmetic and DSP: an LFSR with CRC-8 and CRC-32, a sequential multiplier and divider, CORDIC sine and cosine, a FIR low-pass filter, a CIC decimator for a PDM microphone.

  • CPUs and state machines: traffic lights, a tiny 8-bit CPU, a small RISC-V (RV32I) computer written for the page that prints over the UART, and a Brainfuck CPU.

  • Testbench techniques: self-checking with tasks and a reference model, constrained-random testing with a scoreboard and coverage, and test vectors read from a file.

Download sizes and speed

Each tool downloads from jsDelivr the first time you use it and is then kept in the browser’s cache storage (Clear cache removes it). Compressed download sizes, measured:

Tool Download Notes

Icarus Verilog

1.1 MB

three programs: preprocessor, compiler, vvp

Yosys

14.2 MB

80 MB unpacked; synthesis for every family

nextpnr-ice40

19–61 MB

the tools are 1 MB; the rest is one chip database: 18 MB for HX1K/LP1K/LP384, 34 MB for UP5K/UP3K, 61 MB for the 4K/8K parts and U4K (icepack needs none)

nextpnr-ecp5 + ecppack

9.4 MB

all ECP5 sizes and the Trellis database

nextpnr-himbaechel (Gowin)

3.4–6.9 MB

@yowasp/nextpnr-himbaechel-gowin 0.11.825: 0.7 MB of program and the die’s chip database (they compress well: all ten are 10.2 MB)

gowin_pack (Apicula)

19 MB

Apicula’s wheel and device data (10.2 MB, from the same package) and Python: Pyodide 0.27.7 with numpy, msgspec and lzma (8.8 MB)

nextpnr-nexus + prjoxide

2.9 MB

@yowasp/nextpnr-nexus 0.11.825

nextpnr-machxo2 + ecppack

11–29 MB

@yowasp/nextpnr-machxo2 0.11.825; the MachXO3LF-6900 database is the big one

Schematic (netlistsvg + ELK)

1.1 MB

netlistsvg 1.0.2, elkjs 0.12.0

Once loaded the tools are quick: on a 2023 laptop, blinky synthesises in about 1 s, places and routes for the iCE40UP5K in under 1 s and packs in 0.1 s; the Tang Nano 9K’s place and route takes about 5 s and gowin_pack 3 s; the example testbenches simulate in well under a second. The first run also spends a few seconds compiling the WebAssembly.

Linking to an example

A Share link for an unmodified example names it; for your own design the link carries the project’s files (packed, so keep it small). Opening a link adds the design to your projects.

Parameter Meaning

example

blinky, counter, pwm, knight-rider, gates, debounce, rotary, sevenseg, stopwatch, reaction, freq-counter, servo, stepper, uart, uart-leds, spi-master, spi-slave, i2c-eeprom, ps2, ws2812, vga, vga-bars, vga-ball, vga-text, pong, life, tmds, audio, fifo, async-fifo, dual-port-ram, sdram, lfsr-crc, muldiv, cordic, fir, cic, traffic, cpu, rv32i, brainfuck, tb-tasks, tb-random, tb-files

board

icebreaker, icestick, tinyfpgabx, upduino3, fomu, ulx3s, orangecrab, colorlighti5, tangnano1k, tangnano4k, tangnano9k, tangnano20k, tangprimer20k, tangprimer25k, crosslinknx, machxo3lf, arty, basys3, nexysa7, cmoda7, zyboz7, de10lite, de0nano — any board for a portable example

For example the UART echo on the Tang Nano 9K with its testbench, the RISC-V computer on the ULX3S or VGA colour bars on the Basys 3, ready to export for Vivado.

Limits

  • Xilinx and Intel are synthesis only. openXC7 (nextpnr-xilinx with Project X-Ray’s database) has no WebAssembly build, and there is no open place and route for Intel parts at all; Yosys’s mapping checks the design and estimates resources, and the exported project builds in Vivado or Quartus Prime Lite. Yosys’s Intel flow cannot map block RAM that has initial contents ($readmemh, initial loops); Quartus can, so the exported project is fine.

  • Gowin: gowin_pack runs Apicula 0.32 in Pyodide. YoWASP’s own launcher for it fails (it asks for fastcrc, which has no Pyodide build), so the page installs Apicula from the same wheel without it — slower checksums, same bitstream. nextpnr needs every port of a Gowin design constrained. On the GW5A-25A (Tang Primer 25K) the SSPI configuration pins are always freed as GPIO.

  • CrossLink-NX: Yosys 0.70’s carry chains (CCU2) and nextpnr-nexus 0.11 disagree about a constant carry-in, so the page synthesises with -noccu2 (adders in LUTs: correct, a little slower), and it routes with --router router1, because the default router cannot always reach the global clock buffer from the evaluation board’s clock pin. Every port must be constrained.

  • MachXO: nextpnr-machxo2 knows the MachXO2-640U/1200 and MachXO3(L/LF)-4300/6900 dies only (not the 7000-LUT MachXO2 Breakout’s) and upstream calls it experimental. The MachXO3LF kit’s LED polarity is not stated in its user guide.

  • VHDL is not available. Yosys reads VHDL through the GHDL plugin, and there is no WebAssembly build of GHDL in YoWASP (Yosys here reports No such command: ghdl). Use Verilog or SystemVerilog.

  • SystemVerilog is what Yosys and Icarus Verilog each support: modules, logic, always_ff/always_comb, packed structs and enums are fine; classes, interfaces with modports (in Icarus), assertions and UVM are not.

  • Simulation stops after 30 seconds: a testbench must call $finish. Waveforms of very long runs (tens of megabytes of VCD) are slow to draw; dump only what you need.

  • Vendor primitives (SB_PLL40_PAD, EHXPLLL, rPLL, …) synthesise, but Icarus has no models for them, so simulate the logic around them (the iCEBreaker VGA example’s testbench does).

  • Board pin lists are shared with the FPGA calculators and come from each board’s official constraint files, with those files' port names: the iCEBreaker and iCEstick examples, TinyFPGA BX pins.pcf, UPduino v3.0 upduino.pcf, Fomu fomu-pvt.pcf, ULX3S ulx3s_v20.lpf, OrangeCrab orangecrab_r0.2.pcf, the LiteX Colorlight i5 v7.0 platform; Sipeed’s example CSTs and schematics for the Tang boards; Digilent’s master XDC files; Terasic’s System Builder QSF files (copies on GitHub, checked against the user manuals); and the LiteX platforms for the Lattice evaluation kits, checked against Lattice’s user guides. Each board’s pin list in the Bitstream tab links its sources. The UPduino’s 12 MHz clock reaches pin 20 only with its OSC jumper shorted, the CrossLink-NX board’s 12 MHz clock needs JP2, and its UART the 0 Ω resistors R15 and R17. Check your board’s revision before driving pins.

  • The video examples need a pixel clock near 25 MHz: they run on 25, 27, 50 and 100 MHz boards (the ULX3S through a VGA adapter on its GPIO header); the iCEBreaker has its own VGA example with a PLL. A real HDMI output needs the vendor’s serialiser primitives, which the TMDS example leaves to you.

  • WebAssembly tools are single-threaded and a few times slower than native ones; very large designs (tens of thousands of LUTs) take minutes, and a phone may run out of memory with the bigger chip databases (iCE40 8K, MachXO3LF-6900).

  • Projects stay in this browser only; export a zip to keep or move them.

Related: HDL trainer (learn Verilog step by step), FPGA calculators (PLLs, video timings, constraints), logic analyser (open the VCD), logic simulator, circuit simulator, board pinouts, MCU timing.

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