Links, optics and energy per bit
Bandwidth and energy per bit for PCIe 4–7, NVLink 4–6, NVLink-C2C, CXL, UALink, InfiniBand and Ethernet, one way or both; watts per port to pJ/bit and fleet megawatts for copper, pluggable, linear-drive and co-packaged optics; PAM4 symbol rate and Nyquist frequency; transfer times; and the HBM → DDR → CXL → NVMe memory ladder.
Added
How to use it
How to use it
Links — every link in one table with its source: bandwidth each way and both ways, energy per bit, and signalling. Pick two to compare; the Count switch flips every number between one direction and the sum of both. The ratio does not change — NVLink-C2C’s 900 GB/s against PCIe 5.0 x16’s 128 GB/s is 7 ×, the same as 450 against 64 — but mixing conventions (900 against 64) is the commonest mistake in interconnect arithmetic. Energy figures marked est. are typical for that generation of SerDes, not published numbers.
Optics & power — type a port’s watts and speed to get pJ/bit (W ÷ Gb/s × 1000: 15 W at 800 Gb/s is 18.75 pJ/bit), or press a technology to fill it in. Give a port count and a second wattage to see the fleet in megawatts: 15 W → 5 W across a million ports is 15 MW → 5 MW. PUE scales IT power to facility power.
PAM4 & lanes — a lane’s line rate and modulation give its symbol rate (Gb/s ÷ bits per symbol), Nyquist frequency (half the symbol rate) and unit interval; the waveform shows the same bits as NRZ or PAM4. Lanes × rate gives the aggregate, optionally counting both directions.
Transfer time — a payload over any link, several in parallel, with a latency and an efficiency, and the same payload over every other link for comparison.
Memory tiers — HBM, DDR5, CXL-attached and pooled DRAM, NVMe and networked storage on one latency–bandwidth chart, with capacity and the time to read a given amount from each.
Limits
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Bandwidths are nominal signalling rates; encoding, FLIT framing and protocol headers take 2–10 %. Set the efficiency on the Transfer tab to match a measurement.
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Energy per bit varies with reach, process and what is counted (SerDes only, or retimers, DSP and optics too). The published figures are NVIDIA’s 1.3 pJ/bit for NVLink-C2C and the optics vendors' watts per port; the rest are labelled estimates.
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Memory-tier latencies are typical load-to-use ranges, not guarantees; the pooled-CXL row is an estimate.
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Specifications as of October 2026.
Related: collectives and cluster topology (what these links carry), AI hardware calculator, latency numbers, speed test.
Companion to a spectrum of interconnect, photonics, co-packaged optics and silicon photonics, CXL and tiered memory and the photonic frontier of _AI Acceleration: From Transistors to Trillion-Parameter Models.
Sources
Each row of the Links and Memory tiers tables names its source. Also:
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NVIDIA, Grace Hopper Superchip Architecture In-Depth — NVLink-C2C at 900 GB/s, 7 × PCIe 5.0 x16, 1.3 pJ/bit.
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PCI-SIG, PCI Express specifications; D. Das Sharma, PCIe 6.0: 64 GT/s, PAM4, 256-byte FLIT.
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SemiAnalysis, Co-Packaged Optics: Scaling with Light (2025) — 800G pluggable ≈ 15 W.
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Broadcom, Tomahawk 6 – Davisson (Oct 2025) — 3.5 W per 800G; Bailly 5.4 W.
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Lightmatter, Passage M1000 (2025).
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The Next Platform, Just How Bad Is CXL Memory Latency? (2022).
Linking to an example
Every setting can be written into a link by hand. Put the tab after : links, optics,
signal, transfer or memory; with example= and no , the example’s own tab opens. Sizes
take SI units (140GB, 25MB, 1TiB); in a URL write ` as `%2B`, although a ` typed into the
address bar is understood.
| Parameter | Meaning | Example |
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one of the presets below; parameters written beside it override it |
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links: |
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links to compare: |
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optics: watts per port, port speed in Gb/s |
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optics: ports in the fleet, comparison watts, PUE |
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signalling: Gb/s per lane; |
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signalling: lane count; |
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transfer and memory: payload size |
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transfer: a link id above, a memory tier ( |
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transfer: links in parallel, custom GB/s, latency in µs, efficiency % |
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Presets:
example= |
Shows |
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NVLink-C2C against PCIe 5.0 x16: 7 ×, both ways (open) |
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PCIe 4.0 against 6.0 (256 GB/s both ways at x16) (open) |
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PCIe 5.0 x16 is 64 GB/s each way, not in total (open) |
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NVLink 5’s 1.8 TB/s ≈ 14 × PCIe 5.0 x16 (open) |
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PCIe 5.0 on the host side, 128 GB/s both ways (open) |
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CXL 3.x on the PCIe 6.0 PHY against CXL 2.0 (open) |
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A UALink 200G x4 port against NVLink 5 (open) |
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NVLink 5 against an 800 Gb/s InfiniBand port (open) |
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15 W at 800 Gb/s = 18.75 pJ/bit (open) |
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Linear-drive optics at 8–10 W: 10–12.5 pJ/bit (open) |
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Active copper at 4–6 W (open) |
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CPO at 5.5 W against 15 W: ~3 × (open) |
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Bailly: 5.4 W per 800G = 6.75 pJ/bit (open) |
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Davisson: 3.5 W per 800G = 4.4 pJ/bit (open) |
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15 → 5 W per port across a million ports: 10 MW saved (open) |
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224 Gb/s PAM4: 112 GBd, Nyquist ≈ 56 GHz (open) |
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PCIe 6.0: 64 GT/s PAM4 at a 16 GHz Nyquist (open) |
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PCIe 5.0: 32 GT/s NRZ, also 16 GHz (open) |
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1,024 × 56 Gb/s = 57.3 Tb/s one way (open) |
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Counting both directions: 114.7 Tb/s (open) |
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Eight 400 Gb/s NICs = 3.2 Tb/s; a 1 TB checkpoint (open) |
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A 2 TB checkpoint to eight Gen5 NVMe drives (open) |
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The memory ladder, reading 1 GB from each tier (open) |
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A 64 MB KV-cache block from CXL against NVMe (open) |
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