Decoupling and PDN planner

A power delivery network (PDN) has one job: keep the rail within its ripple budget while the chip’s current jumps. That makes it an impedance problem — the network’s |Z| has to stay under a target impedance from DC up to the frequencies in the current edges — and this tool plans it.

How to use it

Pick the chip (or enter the rail voltage, allowed ripple, current step and its rise time). The tool works out the target impedance Z_t = ΔV/ΔI and the knee frequency 0.35/t_r, the top of the band it checks.
Edit the capacitor bank on the first tab: count × value × package (0201 to 1206 MLCCs, tantalum, aluminium electrolytic, polymer), dielectric and rated voltage. ESR and ESL left blank use typical values for the package; the table below shows each group’s capacitance after DC-bias derating, its total ESL and its self-resonant frequency.
Set the regulator, planes and package on the second tab: the regulator’s output resistance and loop bandwidth, the overlap area of the power/ground planes, and — for FPGAs and SoCs — the package inductance and on-die capacitance, which moves the check to the die.
Describe the mounting on the third tab: the stackup (the same typical boards as the stackup tool) and the via pattern. Every mounting style is tabulated for every package so you can see which change matters.
Read the plot. Each group is drawn on its own (|Z|/n), with the regulator and planes, the combined network in bold, the target as a dashed line and the band checked shaded. Circles mark the anti-resonance peaks; red ones break the target, and the table below names the two parts that cause each one. Hover or tap for a readout.
Auto-suggest finds a small bank that meets the target with the same regulator, planes and mounting, and compares it with the classic one 100 nF per power pin plus a 10 µF. Use this bank copies it into the editor.
Layout advice draws good and bad mounting (top view and cross-section) with their inductance on your stackup.

The model

Target impedance and band. Z_t = V·ripple/ΔI is the flat-target method (Larry Smith, Istvan Novak). The band runs from 100 Hz to the knee frequency 0.35/t_r (Eric Bogatin’s rule for the bandwidth of an edge); set Check up to to override it — on a real board the planes, package and die take over above a few hundred megahertz whatever you place.
Capacitors. Each part is ESR + jω·ESL + 1/(jωC); n identical parts in parallel are Z/n, and the network is every group, the regulator, and the planes in parallel. Typical ESL by package (part on a test fixture): 0201 0.25 nH, 0402 0.4 nH, 0603 0.6 nH, 0805 0.8 nH, 1206 1.0 nH, MnO₂ tantalum 2 nH, SMD aluminium electrolytic 4 nH, polymer 1.5 nH. Typical ESR at resonance is a rough fit to datasheet curves: MLCC ≈ 10 mΩ·(1 µF/C)^0.3 (more in small cases), tantalum ≈ 0.9 Ω·√(10 µF/C), electrolytic ≈ 0.5 Ω·(100 µF/C)^0.6, polymer ≈ 20 mΩ·(100 µF/C)^0.3. All are typical: put a datasheet value in the ESR or ESL box to override.
DC bias. X5R and X7R capacitance falls with DC voltage; the curve C/C₀ = 1/(1 + (V/V_h)^1.7), with V_h a fraction of the rated voltage that grows with case size, is the same approximate typical shape as the Capacitors tool. Real parts vary a lot by series: use Murata SimSurfing, TDK SEAT or KEMET K-SIM for a design. C0G does not change.
Mounting inductance. Added to every capacitor’s ESL: two pad-to-via traces at height h over the first plane, L′ ≈ (µ₀/2π)·ln(1 + 2πh/w) per length, plus the power/ground via pair down to the farther plane of the pair, L = (µ₀·h_via/π)·ln(s/r) (0.4 nH per mm of depth × ln(spacing / barrel radius)), divided by the number of pairs. These are standard closed forms (Bogatin, Signal and Power Integrity — Simplified; Novak, Power Distribution Network Design Methodologies), good to perhaps 20–30%; they ignore the mutual inductance between via pairs and the spreading inductance from the capacitor to the pin.
Regulator. Flat output resistance R up to its loop bandwidth, inductive above: Z = R + jω(R/(2π·f_bw) + L_connection).
Planes. C = ε₀·ε_r·A/d, an ESR from the laminate’s loss tangent (0.02), and the radial spreading inductance (µ₀·d/2π)·ln(R/r) from a via to the edge of a round plane of the same area. Cavity resonances (the first near c/(2√ε_r·side)) are not modelled.
Package and die. With them on, the die sees C_die ∥ (R_pkg + jωL_pkg + Z_board), and the target is checked there. That puts the die–package resonance in the plot — the reason FPGA and SoC makers put capacitors on the package itself.
Anti-resonance. Between two capacitors' resonances one is inductive and the other still capacitive, and they form a parallel tank at ω² = (1/C₁ + 1/C₂)/(L₁ + L₂), with a peak of about X²/(R₁ + R₂). Low ESR makes the peaks taller, which is why a bank of identical low-ESR parts can behave better than a spread of values, and why slightly lossy bulk capacitors help.
Auto-suggest. A greedy search: starting from the regulator, planes and package, it adds the one standard part (1 nF–47 µF MLCCs in their usual packages at about twice the rail voltage, polymer, tantalum and electrolytic bulk) that most reduces Σ max(0, ln(|Z|/Z_t))² across the band per unit cost (bulk parts count as three), until the target is met, then removes any part that is no longer needed. It is a good starting bank, not a proven optimum.

The chip presets are representative, not datasheet values: the RP2040 IOVDD with six pins; an ESP32 at 3.3 V with 350 mA Wi-Fi transmit bursts (a bulk-capacitance problem — brown-out resets are the symptom); an STM32F4 at 168 MHz (ST’s AN4488 asks for 100 nF per VDD pin and one 4.7 µF); a 1.0 V ±3% FPGA core with a 1 A step (a 30 mΩ target, where the stackup and mounting decide everything); and the 5 V input of a CM4-style module. Use your chip’s measured or published current profile for a real design.

A lumped model sees one network, but the board does not: a pin far from every capacitor still has the plane’s spreading inductance to it, so spreading capacitors around the chip and giving every pin a short path remains good practice even when the plot says fewer would do.

Share link copies a URL that opens this tool with your current settings — every value it remembers between visits, packed into ?s=. Opening a link replaces your saved settings for this tool. You can also write a short link by hand with chip (atmega, rp2040, esp32, stm32f4, fpga or cm4), for example /tools/decoupling/?chip=fpga.

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How to use it

The model

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