PCB fab rules for KiCad

Every fab publishes a page of what it can make, and every new KiCad project starts with KiCad’s own defaults, which are not any fab’s. I kept typing the same numbers into Board Setup from memory. This page writes them out for the fab and service I am ordering from, as a rules file KiCad’s DRC reads, and checks a finished board against them.

How to use it

Choose the fab and its service. JLCPCB has 1–2 layer and 4–6 layer boards in 1 oz and 2 oz copper; PCBWay has its standard 1 oz and 2 oz figures and its tightest (extra cost) ones; OSH Park has its 2-layer and 4-layer services. The line under the choices gives the main numbers and a link to the fab’s page.
Board thickness lists the thicknesses that service offers. It goes into the rules file’s header and the Board Setup table.
Margin adds the same amount to every minimum, if you would rather not design right at the fab’s limit. 0.02–0.05 mm is plenty.
Standard-price vias holds vias to a size the fab makes without a surcharge, instead of its smallest. Each fab’s reason is on the Board Setup tab.
V-scored edges uses the copper-to-V-score clearance (JLCPCB: 0.4 mm) instead of the routed one.
Rules file: download the .kicad_dru or copy it. Save it beside the .kicad_pro with the same name (myboard.kicad_dru), or paste it into Board Setup → Design Rules → Custom Rules. It holds track width, clearance, via hole, diameter and ring, plated and non-plated hole sizes, slot widths, hole-to-hole spacing, copper to edge, silkscreen to pads and silkscreen text size, each as a named rule, with a header saying where the numbers came from.
Board Setup: the same numbers by the names KiCad 8 and 9 give the fields in Board Setup → Design Rules → Constraints, plus the solder mask web and the stack-up. Custom rules work on top of these: DRC flags anything that breaks either, so set both.
Net classes: Default (0.2 mm tracks and gaps, the standard-price via), Power (a width for the current you set, from IPC-2221 with a 10 °C rise), Fine pitch (the fab’s minimums) and USB (a differential pair: its width and gap depend on your stack-up).
Check a board: open a .kicad_pcb, take the board last opened in the board viewer, or try the sample. It is drawn with its copper and outline, and every finding is a ring on the board and a line in the list. Click either one to go to it. Change the fab, service or margin and the check runs again.
Compare fabs: every service’s numbers side by side. A dash means the fab does not publish that figure. A star means the fab adds a condition: hover to read it.

Where the numbers come from

Each fab’s own page, checked on 2026-11-03. They change, so check the page before you order.

JLCPCB: PCB capabilities. Tracks and gaps 0.1 mm on 1–2 layer 1 oz, 0.09 mm on multilayer 1 oz, 0.16 / 0.15 mm on 2 oz. Via 0.15 mm hole on a 0.25 mm pad. JLCPCB charges more for 0.1 and 0.15 mm holes, and for 0.2–0.25 mm holes with a pad under 0.45 mm. PTH ring 0.18 mm absolute minimum on 2-layer (0.25 recommended) and 0.15 mm on multilayer (0.2 recommended), 0.254 mm with 2 oz. Holes 0.15–6.3 mm. Hole to hole 0.2 mm between vias and 0.45 mm between pad holes. NPTH 0.5 mm. Slots 0.5 mm plated (0.35 on multilayer) and 1.0 mm non-plated. Copper to a routed edge 0.2 mm and to a V-score 0.4 mm. Mask bridge 0.1 mm. Silkscreen lines 0.15 mm, text 1.0 mm high, 0.15 mm from pads.
PCBWay: PCB capabilities. The page gives a "normal" and a "medium difficulty" figure for many rows. The standard service here uses the normal ones: 5 mil tracks and 6 mil gaps on 1 oz outer layers, 7/8 mil on 2 oz, holes from 0.3 mm (0.15 mm costs more). The tightest service uses the page’s headline 4/4 mil and 0.15 mm, which cost extra. Ring 0.15 mm, holes to 6.0 mm, 16 mil between component holes and 11 mil between vias, slots 0.5 mm plated and 0.8 mm non-plated, 0.25 mm from a routed edge, a 4 mil mask bridge, and silkscreen 0.15 mm lines and 0.8 mm text. PCBWay does not publish a V-score clearance or a smallest NPTH.
OSH Park: 2 layer and 4 layer. 6/6 mil (2-layer) and 5/5 mil (4-layer), 10 mil drills, rings of 5 mil and 4 mil, 15 mil from the edge, 20 mil slots. The 4-layer page adds a 4 mil mask web, 5 mil silkscreen lines and 10 mil from a plated hole to inner copper. OSH Park does not publish hole-to-hole, largest drill or V-score figures.

Aisler is not included. Its design rules moved to its community forum, and the post I could read gives only track, gap and drill figures from 2021.

The Gerber viewer and DFM check reads the same table (fab-rules-core.js), so the two pages always agree.

What the check looks at

Track widths, via holes, via diameters and via rings.
Pad holes: plated and non-plated sizes, slot widths, holes over the largest drill, and PTH rings.
Hole to hole, edge to edge, between vias and between holes of different footprints.
Copper (tracks, pads and vias) to the board outline, cut-outs included.
Copper to copper of different nets on the same layer, as the board viewer measures it.
Silkscreen text height and stroke.

Limits

It is a quick check against the published numbers, not KiCad’s DRC. Zone fills, thermal reliefs, solder mask and silkscreen overlap are not checked. Put the rules file in the project and run DRC (Inspect → Design Rules Checker) for the real thing.
Arcs are short straight pieces and custom pads their primitives, so a gap can be off by a few microns.
Blind and buried vias are checked like through vias. Micro-vias are skipped.
The Power class width is IPC-2221 for an outer layer, which is conservative. The trace width calculator does inner layers and other temperature rises.
I tested the rules files with KiCad 9.0.2’s kicad-cli pcb drc: every service’s file loads, and a deliberately tight one makes DRC report each kind of rule (track width, clearance, hole size, ring, via diameter, hole to hole, edge clearance, silkscreen clearance, text height and thickness).

Privacy

Everything happens in your browser. A board you open is read from the file and not kept. The board from the viewer comes from this browser’s storage, where the board viewer left it.

Linking to an example

Share link copies a URL with the fab, service and options. It never includes a board.

Parameter Meaning

Parameter	Meaning
`example`	A preset (below)
`fab`	`jlcpcb`, `pcbway` or `oshpark`
`svc`	The service: `2l-1oz`, `2l-2oz`, `ml-1oz`, `ml-2oz` (JLCPCB); `std-1oz`, `std-2oz`, `min-1oz` (PCBWay); `2l`, `4l` (OSH Park)
`thick`	Board thickness, mm
`margin`	Margin added to every minimum, mm
`cheap`	`true`: hold vias to the standard-price size
`vcut`	`true`: use the V-score edge clearance
`amps`	Current for the Power net class, A

example

A preset (below)

fab

jlcpcb, pcbway or oshpark

svc

The service: 2l-1oz, 2l-2oz, ml-1oz, ml-2oz (JLCPCB); std-1oz, std-2oz, min-1oz (PCBWay); 2l, 4l (OSH Park)

thick

Board thickness, mm

margin

Margin added to every minimum, mm

cheap

true: hold vias to the standard-price size

vcut

true: use the V-score edge clearance

amps

Current for the Power net class, A

Presets: JLCPCB 1–2 layer · JLCPCB 4–6 layer · JLCPCB with standard-price vias · PCBWay standard · OSH Park 4 layer · check the sample board against OSH Park 4 layer.