Chris Collins

Tools · fpga

HDL trainer: learn Verilog by doing

Learn Verilog by writing it: 23 lessons from gates to UARTs, VGA timing, FIFOs and pipelines, each checked by a hidden testbench that simulates your module and shows the waveform and every mismatch — plus a sandbox simulator and a logic-sim → Verilog converter.

Added · updated 28 October 2026

Works with

How to use it

A Verilog course that runs in your browser. Each lesson explains one idea, gives you starter code with something missing or wrong, and checks your module with a hidden testbench: the bench drives every input cycle by cycle, compares every output with a reference model, and shows you the waveform with each failed check marked, a table of expected against actual values, and lint warnings (latches, blocking assignments in clocked blocks, signals driven from two places).

The simulator is written for this page: an event-driven Verilog simulator for the synthesizable subset with the standard’s scheduling rules (active, inactive and non-blocking-assignment regions), four-state values (0, 1, x, z), and the standard’s rules for expression width and signedness. Its results are checked against Icarus Verilog: a set of semantic test benches, and every lesson’s stimulus replayed against the solutions and the common mistakes, agree bit for bit.

How to use it

  • Course: pick a lesson, read the explanation on the left, edit the code on the right and press Run tests (or Ctrl/⌘ + Enter). Green means every check passed and the lesson is marked done; red lists the failed checks — click a time in the waveform or a line link to find the problem. Hint reveals hints one at a time; Show solution replaces your code. Your code for each lesson and your progress are saved in this browser only.

  • Waveform: buses show their value (hex or decimal), x is red, z (nothing driving) blue. Drag to pan, Ctrl/⌘ + wheel or the buttons to zoom, hover for exact values. Failed checks are red ▲ marks; hovering one shows what was expected.

  • Sandbox: write any design plus a testbench (initial, # delays, @(posedge clk), $display, $monitor, $finish) and run it; the top module is the one nothing instantiates. Download VCD saves the waveform for GTKWave or the logic analyzer. To sandbox in a lesson copies your module there with a testbench skeleton.

  • Synthesise (in a lesson or the sandbox) runs Yosys on your module — the real tool, compiled to WebAssembly, borrowed from the FPGA playground and loaded only when you press it (about 14 MB the first time, then cached). Pick iCE40 UP5K, ECP5 25k or generic 4-input LUTs and see the LUTs, flip-flops and carry cells it needs and the schematic (RTL or gate level) — pan, zoom, click a part for its connections, search, resize it with its grip, ⛶ Full or ⧉ Pop out into its own window, which follows each new synthesis. It uses the module’s default parameters, not the lesson bench’s. Open in FPGA playground takes your code there as a new project, to pick a board, place and route and make a bitstream.

  • From logic-sim: converts a circuit from the digital logic simulator — the one you have open there, an example, or an exported JSON file — into structural Verilog (gates become assign, flip-flops always @(posedge …), RAM and ROM arrays). Check it in the sandbox. The conversion is tested by simulating both and comparing every output.

  • Full screen (the ⛶ button, or F) gives the editor and waveform the whole screen; ◫ Panels hides the lesson text.

The lessons: gates; vectors and concatenation; multiplexers; adders and hierarchy; signed comparison and expression width; always @* and case (a 7-segment decoder); unintended latches; flip-flops with reset and enable; blocking vs non-blocking; synchronous and asynchronous reset; counters and clock enables; Moore and Mealy state machines; synchronisers and edge detection; debouncing; LFSRs; UART transmit and receive; PWM; 7-segment multiplexing; VGA timing; a FIFO; and a pipelined multiply-add.

Linking to an example

A link can open a lesson: add ?lesson= and the lesson id. Your code and progress never go into a link.

Parameter Meaning

lesson

Lesson id, e.g. nonblocking, moore, uart-tx, vga, fifo. The tab travels in the #hash: #course, #sandbox, #logic-sim.

Examples: blocking vs non-blocking, the UART transmitter, VGA timing.

Limits

  • Verilog-2005 subset: no tasks, inout ports, real numbers, defparam, generate case, multi-dimensional arrays, user-defined primitives or specify blocks; $random is a simple deterministic generator, not Icarus' sequence. A few SystemVerilog conveniences work (logic, always_ff, always_comb, +`, `=).

  • Zero-delay simulation only: # delays in testbenches work, but there are no gate or wire delays, so a logic-sim circuit that relies on gate delay (a ring oscillator) does not settle.

  • Following Icarus Verilog, declaration initialisers (reg q = 0;) apply before time 0 and wake @(…) waits once; always @* blocks also run once at time 0 (like always_comb).

  • Simulation is not synthesis: the lint catches common mistakes, but code that simulates can still fail to synthesise — press Synthesise to find out. The FPGA calculators help with timing, PLLs and pins.

Related: FPGA playground, FPGA calculators, digital logic simulator, Boolean logic, logic analyzer, MCU timing.

Runs entirely in your browser; nothing you type leaves this page.