Transmission lines and reflections

When a signal’s edge is short compared with the time it takes to travel down a wire, the wire stops being "a connection" and becomes a transmission line: the edge travels as a wave, and every change of impedance — the far end, a connector, a via, a branch — sends part of it back. The result is the overshoot, ringing and stair-stepped edges you see on a scope. This tool lets you watch it happen and work out what to do about it.

How to use it

Bounce simulator — pick a preset (Arduino GPIO, fast LVCMOS, DDR3, USB, long cables, or the textbook matched, open, short and 2:1 cases), or set the source (step, pulse or clock; rise time; resistance), the line (Z₀, and a delay or a length with velocity factor; optional loss) and the load. Press Play to watch the voltage travel along the line, with its forward and backward waves. Below it are the waveforms at both ends, a space–time waterfall in which every edge is a diagonal, and — for resistive loads — the lattice diagram and a table of every arrival.
TDR — build an impedance profile from the port outwards: lines (Z₀, length, εeff), shunt capacitors (pads), series inductors (vias, bond wires) and open stubs, ending in a matched load, a resistor, an open or a short. The plot shows what a time-domain reflectometer with your rise time would display, against the true profile, and the table lists Γ at each step.
Termination — set a driver, a line and a receiver and the clock rate. The tool runs the same clock through no termination, series, parallel, Thevenin, AC and Schottky-clamp termination, and shows each waveform at the receiver, the overshoot, undershoot, ringback, settling time, levels, delay and power, with recommendations.
Is it a line? — enter a rise time (or pick a signal) and the board or cable, and get the knee frequency, the length of the edge on the trace and the critical length below which you can treat the trace as a plain wire.

The physics

Reflection coefficient: Γ = (Z_L − Z₀)/(Z_L + Z₀) — +1 for an open, −1 for a short, 0 when matched, +1/3 for a 2:1 mismatch (100 Ω on 50 Ω). A wave arriving at the step continues with 1 + Γ of its voltage and sends Γ of it back.
Launch: a source of open-circuit swing ΔV and resistance Rs launches ΔV·Z₀/(Rs + Z₀) — the line looks like a resistor Z₀ until the first reflection returns.
The lattice diagram follows each wave: it reaches the load after Td, is multiplied by Γ_L, returns to the source after 2Td, is multiplied by Γ_S, and so on. The voltage at an end is the sum of everything that has arrived. For a low-impedance driver into an open end (Rs = 10 Ω, Z₀ = 50 Ω) the load swings to 1.667, then 0.556, 1.296, 0.802 … of the source step: ringing that converges on 1. With a finite rise time each step becomes a ramp; the response is the lattice’s sum of delayed copies of the source waveform, which the tool computes exactly.
Reactive and non-linear loads (capacitors, inductors, R‖C, RC, diodes) have no single Γ: a capacitor looks like a short to a fast edge and an open later. For these the tool solves the telegrapher equations directly by the method of characteristics (Bergeron’s method): the line is a chain of cells one time step long, forward and backward waves move one cell per step, and at each end the load is solved against the line’s Thevenin equivalent (2 × the incident wave behind Z₀) with trapezoidal companion models for C and L and Newton’s method for diodes. For a lossless line this is exact — at that time step it is the same scheme as an FDTD at the "magic" Courant number of 1 — and the tests check it against the lattice diagram to 10⁻¹⁴.
Loss: "attenuation" scales each wave by a fixed factor per pass (a distortionless line, R′/L′ = G′/C′, which keeps the lattice exact). "Series resistance" runs a Yee FDTD of the telegrapher equations with R′ (Paul, Analysis of Multiconductor Transmission Lines, ch. 8): the DC level drops across the cable’s resistance and the edges get a slow tail, as on long twisted pair. Skin effect and dielectric loss, which grow with frequency and round off fast edges further, are not modelled.
TDR: the port is a step behind Zref; the trace is ρ(t) = V/V_incident − 1 and Z = Zref·(1 + ρ)/(1 − ρ). A small shunt C gives a dip of about Z₀C/(2T) and a series L a bump of L/(2Z₀T) for an edge ramping over T; the tool uses the exact (τ/T)(1 − e^(−T/τ)). Past the first discontinuity the displayed impedance is no longer exact — the multiple reflections the tool simulates are the "masking" a real TDR shows too.
Termination values: series R = Z₀ − R_driver; parallel R = Z₀; Thevenin 2Z₀ to each rail; AC R = Z₀ with C ≈ 3 round trips / Z₀ (rounded to E12). Power is integrated from the simulation over one clock period.
When it is a line (Johnson & Graham, High-Speed Digital Design): knee frequency 0.5/t_r; the edge occupies t_r/t_pd of trace; below about a sixth of that (the critical length) reflections merge into the edge and the trace is lumped. Microstrip εeff uses Hammerstad & Jensen.

Presets are typical figures — the ATmega328P’s roughly 25 Ω output, JEDEC DDR3’s 34 Ω driver and RTT = 60 Ω on-die termination, USB 2.0 high speed’s 17.78 mA into 45 Ω per wire — not limits. Driver outputs are modelled as a linear resistance behind an ideal ramp; real CMOS drivers are non-linear, so check critical designs with the IBIS models from the part’s vendor.

PCB stackup and impedance gives Z₀ and the delay per millimetre of your trace; feedline and SWR and the Smith chart show the same reflections at a single frequency; matching networks designs a match at one frequency; PCB traces and vias covers current and resistance.

Share link copies a URL that opens this tool with your current settings — every value it remembers between visits, packed into ?s=. Opening a link replaces your saved settings for this tool.

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How to use it

The physics

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