Chris Collins

Tools · electronics

EMC and ESD protection

Protect and quieten a board: IEC 61000-4-2, HBM and CDM pulses plotted; TVS selection against an interface's working voltage, capacitance budget and the IC's limit; the L·di/dt of a badly placed TVS simulated; series-resistor pin protection; IEC 61000-4-5 and ISO 7637 / load-dump surge energy; a loop-area drawer for radiated emission; a clock's harmonics against CISPR 32; ferrite beads, common-mode chokes, damped LC filters, and a layout checklist.

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How to use it

Two problems with one cause. Electromagnetic compatibility is the board not disturbing its neighbours (emissions) and not being disturbed by them (immunity); ESD and surge protection is it surviving the fast, high currents that people, cables and vehicles inject. Both come down to where fast currents flow and how big the loops they make are. This tool works through each part with the real waveforms and the textbook estimates, and ends with a layout checklist.

How to use it

  1. ESD pulses. Pick an IEC 61000-4-2 level (contact or air) and see the current, with the standard’s checkpoints — first peak 3.75 A/kV, 0.8 ns rise, 2 A/kV at 30 ns and 1 A/kV at 60 ns — checked against the model. Turn on HBM and CDM to compare the component-level tests.

  2. TVS selection. Choose the interface (USB 2/3, HDMI, Ethernet, CAN, RS-485, GPIO, 12/24 V power). Its working voltage and capacitance budget fill in; set the IC’s limit and the ESD level. Every part in the table is checked — standoff, negative standoff, capacitance, clamp voltage at the matching TLP current, ESD rating — and ranked. Add your own part from a datasheet.

  3. Placement (L·di/dt). The ESD current divides between the TVS (behind its stub and via inductance) and the trace to the IC (whose own ESD diode clamps at VDD + a diode). Change the stub inductance, the trace and a series resistor, and watch the voltage and current at the IC pin. The presets show a good placement, a TVS 10 mm away, and the effect of 22 Ω in series.

  4. MCU pin. Size a series resistor so a 24 V (or negative) input keeps the pin’s clamp current within the datasheet’s injection limit, with the RC bandwidth it costs and a back-powering check.

  5. Surge. The IEC 61000-4-5 1.2/50 µs – 8/20 µs combination wave into a TVS (peak current, power and energy against its rating); the ISO 7637-2 pulses and the ISO 16750-2 load dump for 12 V or 24 V vehicles, pulse by pulse; and a 12/24 V input with fuse, reverse-polarity protection and a TVS that must stay off through a jump start yet clamp below the regulator’s absolute maximum.

  6. Loop area. Draw a signal path on the 100 × 60 mm board (click or tap to add corners), then either let it return through a solid plane or draw the return path. The tool gives the loop area and the radiated field against the CISPR 32 limit, and the common-mode cable field for comparison. Use this loop in the clock spectrum carries the area over.

  7. Clock spectrum. A trapezoidal clock’s harmonics radiated from that loop, against the class A and B limits, with the envelope’s corners at 1/(πτ) and 1/(πtr). Try slower edges, a series resistor into the load capacitance, and spread spectrum.

  8. Filters & fixes. A ferrite bead’s impedance with and without DC bias, a common-mode choke’s common- and differential-mode impedance, and an LC, π or bead filter on a power input — its insertion loss, output impedance, resonance peaking, optimum Middlebrook damping and the stability check against a switching regulator’s negative input resistance.

  9. Layout checklist. Eleven rules, each with a short explanation and a good and a bad sketch: return planes, split planes, stitching vias, connector placement, chassis ground, 360° shield bonding, ground loops, TVS placement, board edges, filters at the boundary, and sensitive inputs.

The models

  • IEC 61000-4-2. The contact current is the standard’s own sum of two Heidler functions (Annex B of the 2008 edition): I₁ = 16.6 A, τ₁ = 1.1 ns, τ₂ = 2 ns, I₂ = 9.3 A, τ₃ = 12 ns, τ₄ = 37 ns, n = 1.8 at 4 kV, scaled linearly with the charge voltage. Test levels 1–4 are ±2, 4, 6, 8 kV contact and ±2, 4, 8, 15 kV air. The standard gives no air-discharge waveform; the one drawn is the contact current behind a 2 ns arc lag, an illustration only.

  • HBM and CDM. HBM (ANSI/ESDA/JEDEC JS-001) is 100 pF discharged through 1.5 kΩ: V/1.5 kΩ peak, 150 ns decay, a 2–10 ns rise. CDM (JS-002) is the charged part discharging through its own pin: drawn as an illustrative series RLC (6.8 pF, 10 nH, 40 Ω) — about 7 A at 500 V with a 0.2 ns rise, not a calibrated model of a tester.

  • Capacitance budget. A shunt capacitance on a line of impedance Z₀ sees Z₀/2 and adds a rise of about 2.2·(Z₀/2)·C; the tool shows the C that adds 10 % of a bit time beside the usual recommendation for the interface (≈ 2.5 pF for USB 2.0, 0.5 pF for USB 3 and HDMI 1.4).

  • Clamp voltage. For ESD the clamp is Vbr + RTLP·I at the TLP current that matches the level: 2 A/kV, the IEC waveform’s 30 ns current (16 A for 8 kV, the convention behind datasheets' "clamp at 16 A TLP"). For surge it is Vbr + Rdyn·I with Rdyn = (Vc − Vbr)/Ipp from the datasheet’s 8/20 µs or 10/1000 µs point.

  • TVS parts. USBLC6-2SC6 (ST), TPD4E05U06 (TI), PESD5V0S1BL (Nexperia), NUP2105L (onsemi), SM712 (Semtech/Littelfuse), SMBJ5.0A–33A and SMCJ24A (Littelfuse), SM8S24A (Vishay). The values are typical figures from those makers' datasheets, rounded; the RTLP of the power parts and the capacitance of the SMBJ/SMCJ/SM8S families are estimates. Design from the current datasheet.

  • ESD current sharing. The gun is treated as a current source (its 330 Ω is large next to the clamps) into the connector node; one branch is the TVS’s stub and via inductance then its clamp, the other the trace’s inductance and series resistance to the pin capacitance and the IC’s ESD diode (VDD + 0.6 V plus a few ohms). The four equations are integrated with RK4 at a 1 ps step. A TVS’s stub adds about L × 37 A/ns at 8 kV: 1 nH is ~37 V.

  • MCU injection. I = (Vin − VDD − Vf)/R. ST’s STM32 datasheets give ±5 mA per pin and ±25 mA in total; Atmel’s AVR182 application note keeps an AVR’s clamp current under 1 mA; the RP2040 and ESP32 publish no injection rating, so the tool asks for external Schottky clamps.

  • IEC 61000-4-5. The 1.2/50 µs open-circuit voltage is the standard’s 1.037·(1 − e^−t/0.4074 µs)·e−t/68.22 µs^; the 8/20 µs current is drawn as Ip·(t/3τ)³·e3−t/τ with τ = 3.911 µs (front 8 µs, half value 21.6 µs). The generator is its open-circuit voltage behind 2 Ω (line–line), 12 Ω (line–earth) or 42 Ω (signal lines through the coupling network).

  • Automotive. ISO 7637-2 pulses 1, 2a, 3a and 3b at their level-IV amplitudes and source resistances, and the ISO 16750-2 load dump 5a (12 V: 79–101 V, 0.5–4 Ω, 40–400 ms; 24 V: 151–202 V, 1–8 Ω, 100–350 ms) and 5b (centrally clamped to 35 V or 58 V), each riding on 13.5 V or 27 V. The energy is integrated through the source resistance into the clamp. A TVS’s allowed peak power is its rating scaled by t−½ from its test pulse (the usual slope of "peak pulse power vs pulse time"; 10/1000 µs ≈ a 1.44 ms rectangle) — a rough check; use the part’s curve.

  • Radiated emission. Differential mode, a loop small against the wavelength over a reflecting floor: E = 2.63×10⁻¹⁴·f²·A·I/r V/m; common mode on a cable of length L (capped at λ/4): E = 1.257×10⁻⁶·f·L·I/r (Henry W. Ott, Electromagnetic Compatibility Engineering, Wiley 2009, ch. 12). With a solid plane the loop is the trace length × its height over the plane; without one it is the polygon of the signal and return paths (the shoelace formula).

  • Trapezoid spectrum. cn = 2A·(τ/T)·|sinc(nπτ/T)|·|sinc(nπtr/T)|, bounded by an envelope that is flat to 1/(πτ), falls at −20 dB/decade to 1/(πtr) and at −40 dB/decade beyond (Clayton R. Paul, Introduction to Electromagnetic Compatibility, ch. 3). A series resistor R into a load C stretches the edge to √(tr² + (2.2RC)²). Spread spectrum by δ spreads harmonic n over n·δ·f, a reduction of 10·log(n·δ·f/120 kHz) in the CISPR receiver’s bandwidth.

  • CISPR 32 limits (approximate, check your edition): class B 30/37 dBµV/m quasi-peak at 10 m (30–230 MHz / 230–1000 MHz), 50/54 dBµV/m average at 3 m (1–3 / 3–6 GHz); class A 40/47 and 56/60. Distances are converted by 20·log(r).

  • Ferrite beads and chokes. Rdc + (L ∥ R ∥ C) fitted to typical 0603/0402/0805 curves, with a typical DC-bias shape (half the inductance at about a third of the rated current). Common-mode chokes are the same network in common mode and their leakage inductance in differential mode. Insertion loss is |Zs + Zl + Z|/|Zs + Zl|.

  • Input filters. ABCD matrices of the ladder between the source resistance and the load. A switching regulator’s input is a negative resistance −V²/P; Middlebrook’s condition asks for the filter’s output impedance to stay well below it. The damping branch is Cd = n·C with the optimum Rd = R₀·√2+n)(4+3n)/(2n²(4+n) and peak output impedance R₀·√(2(2+n))/n (Erickson & Maksimović, Fundamentals of Power Electronics, §10.4), R₀ = √(L/C).

These are design estimates for comparing choices: a compliance test measures the whole product, cables and all, and a pre-compliance scan with a near-field probe tells you more than any formula.

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