Digital logic simulator

Each wire carries one of four values: 0, 1, X (unknown — a floating gate input, a flip-flop that has never been set, or a short between a 0 and a 1) and Z (high impedance — nothing is driving the wire, as when every tri-state buffer on a bus is off). Gates follow the usual rules for X: AND with any 0 input is 0 whatever the others are, OR with any 1 is 1, otherwise an unknown input gives an unknown output.

The simulator is event-driven, like the ones chip designers use. With Ideal selected every part switches instantly (in zero time, in "delta cycles"), which is easiest to reason about. With Gate delays on, each part’s output changes its delay ticks after its inputs (1 by default, editable per part), so the Glitch (hazard) example shows the brief false 1 that a slow inverter causes, the 4-bit adder shows its carry rippling bit by bit, and the Ring oscillator oscillates with a period of twice the loop delay. Outputs keep every change (transport delay), so even pulses shorter than a gate’s delay are shown.

A loop with no stable state — an inverter wired to itself, or an odd ring of inverters — cannot settle with ideal gates; the status line says so after 2,000 delta cycles. Turn on gate delays to watch it oscillate.

The timing diagram under the drawing shows every clock, input and output (and any wire you watch) against time in ticks: 1-bit signals as high and low lines, buses as values, X and Z as shaded bands. Download VCD saves it as a Value Change Dump (IEEE 1364, one tick = 1 ns) to open in GTKWave or the logic analyzer.

The Truth table tab lists every combination of the inputs (top to bottom = most significant first, up to 10 bits) and the outputs, simulated from power-on. For each 1-bit output it shows the expression read back through the gates as you built them, and the minimal sum of products and product of sums, found with Quine–McCluskey by the Boolean logic tool; rows that come out X are used as don’t-cares. Karnaugh map in Boolean logic opens that tool on the minimised expression with its K-map drawn and grouped.

The Expression → circuit tab goes the other way: type F = A’B + AB' (one output per line or separated by ;) and it builds switches, gates and LEDs, laid out in columns by depth with shared sub-expressions sharing gates. Choose As written, Minimised SOP (via the Boolean logic tool), or NAND only — every gate turned into NANDs, showing that NAND alone is enough to build any circuit. Notation: NOT A' !A ~A; AND AB A·B A&B; OR + |; XOR ^ ⊕; also NAND, NOR, XNOR, → and <→.

Put Input pin and Output pin parts on a circuit, label them, and on the Components tab choose Save this circuit as a component. It appears in the palette under "My components" as a box whose pins are the pin labels, top to bottom. Components can contain other components; each circuit carries copies of the definitions it uses, so a shared link or an exported file is complete. Double-click a placed component (or Look inside) to open it, then Save and go back. An input pin can say what the inside sees when nothing is wired to it (If unconnected: 0, 1 or floating). When gate delays are on, a component’s inside runs with its own gates' delays; its pins add none.

Pick one from Examples… in the toolbar or from the Files & examples tab:

Each ROM byte is one instruction: the high nibble is the opcode and the low nibble the operand n (0–15). It is a single-cycle machine: on every rising clock edge the instruction at PC executes and PC moves on (or jumps).

The demo program is LDI 0, loop: ADD 3, OUT, JMP loop, so OUT shows 3, 6, 9, C, F, 2 … (4-bit arithmetic wraps). Try LDI 5, l: OUT, SUB 2, JC l, HLT: it counts 5, 3, 1 and halts when the subtraction borrows. Labels end in a colon and ; starts a comment.

The current circuit is kept in this browser automatically. Files & examples saves named copies, exports and imports JSON, and starts a new circuit. Share link (under the title) packs the whole circuit — parts, wires and sub-circuit definitions — into the link, with the gate-delay setting and speed. Your saved circuits and component library are never put in a link.